Re: [PATCH] common: resource: print conflicts as warning

On Mon, Jun 23, 2014 at 10:00:00AM +0200, Alexander Aring wrote: Crazy things happen if there are resource conflicts and a device probe runs dev_request_mem_region. The dev_request_mem_region returns a start pointer which is zero. The probe function doesn't check on this and probing the device

[RFC] incorporate picotcp into barebox

Hi, Daniele! Do you have any progress on introducing barebox-related ping and dhcp client changes into picotcp? --  Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 0/7] Marvell MVEBU assorted fixes and cleanup

On Mon, Jun 23, 2014 at 10:10:28PM +0200, Sebastian Hesselbarth wrote: This patch set comprises cleanup and some fixes for outstanding bugs in Marvell MVEBU SoC support. Patch 1 adds default model and hostname for Dove SoCs. Patch 2 consolidates TEXT_BASE from per-board to per-SoC

[PATCH 1/3] arm: imx6: move imx6_init_lowlevel to single initcall

Instead of repeating the same lowlevel init for every board move it to it's own initcall. Avoids code bloat and shaves off almost 1.5kB of uncompressed barebox size for a default imx_v7_defconfig build. For boards wherethe hostname setup was done in the postcore initcall we move this to a

[PATCH 3/3] scripts: tegra: add gitignore

Keep the git status area clean of generated binaries. Signed-off-by: Lucas Stach d...@lynxeye.de --- scripts/tegra/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 scripts/tegra/.gitignore diff --git a/scripts/tegra/.gitignore b/scripts/tegra/.gitignore new file mode 100644

[PATCH 2/3] arm: imx6: rename hummingboard directory to microsom

The rule in barebox is to name the directories after the modules. As hummingboard is just one of the carriers for the MicroSOM module, name the directory accordingly. Signed-off-by: Lucas Stach d...@lynxeye.de --- arch/arm/boards/Makefile| 2 +-

Re: [PATCH 00/11] Convert MVEBU SoCs to DT and PBL_MULTI_IMAGE

On Mon, Jun 23, 2014 at 10:10:51PM +0200, Sebastian Hesselbarth wrote: This patch set converts Kirkwood and Armada 370/XP to DT and provides PBL_MULTI_IMAGE support as we already have for Dove. Patch 1 resorts pbl entries in arch/arm/dts/Makefile back to alphabetical order. Patch 2

Re: [PATCH 5/7] i2c: i2c_gpio: add devicetree support

On Tue, Jun 24, 2014 at 01:21:11AM +0400, Antony Pavlov wrote: Signed-off-by: Antony Pavlov antonynpav...@gmail.com --- .../devicetree/bindings/gpio/gpio_i2c.txt | 32 + drivers/i2c/busses/i2c-gpio.c | 54 +++-- include/of_gpio.h

Re: [PATCH 0/7] MIPS: malta: enable gpio i2c stuff

On Tue, Jun 24, 2014 at 01:21:06AM +0400, Antony Pavlov wrote: Antony Pavlov (7): gpio: add Malta CBUS FPGA I2C driver MIPS: add asm/gpio.h header file MIPS: malta: enable gpiolib MIPS: dts: qemu-malta.dts: enable CBUS FPGA I2C gpio driver i2c: i2c_gpio: add devicetree support

Re: [PATCH 1/3] arm: imx6: move imx6_init_lowlevel to single initcall

On Tue, Jun 24, 2014 at 08:33:14AM +0200, Lucas Stach wrote: Instead of repeating the same lowlevel init for every board move it to it's own initcall. Avoids code bloat and shaves off almost 1.5kB of uncompressed barebox size for a default imx_v7_defconfig build. For boards wherethe

Re: [RFC] incorporate picotcp into barebox

On Tue, Jun 24, 2014 at 8:18 AM, Antony Pavlov antonynpav...@gmail.com wrote: Hi, Daniele! Do you have any progress on introducing barebox-related ping and dhcp client changes into picotcp? -- Best regards, Antony Pavlov Hello Antony, Yes, I've been working on the components themselves

[PATCH 3/4] net: orion-gbe: extend RGMII detection to delayed modes

RGMII PHY modes include delayed interface modes RGMII_ID, RGMII_TXID, and RGMII_RXID. Also check for those modes when setup RGMII mode in port serial ctrl register. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org ---

[PATCH 2/4] net: orion: generate unique port device names

Marvell Orion ethernet IP originally is multi-port capable, but SoCs using the IP usually have multiple single-port controllers built in. Currently, orion-gbe driver registers each port device with a constant name, which causes a name conflict with multiple controller instances. This patch

[PATCH 1/4] of: net: respect phy-connection-type property

ePAPR defines phy-connection-type as standard property for PHY interface between Ethernet device and PHY device. Add corresponding property check to of_get_phy_mode. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org --- drivers/of/of_net.c |

[PATCH 0/4] Orion GBE fixes and Marvell PHY driver

This patch set comprises some fixes and improvements related with ethernet support on Marvell Orion SoC based boards. Patch 1 adds a check for ePAPR standard phy-connection-type property to of_get_phy_mode. Patch 2 resolves a device name conflict on orion-gbe port names when using more than one

[PATCH 4/4] net: phy: add support for Marvell PHY drivers

This adds initial support for Marvell PHY specific drivers. As a first PHY, a driver for MV88E1121R is ported over from Linux. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org --- drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile

[PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register

As stated in section 29.19.35 of SAMA5D3 Series Datasheet, MODE register has offset 0x10 and at offset 0x0C there is a TIMINGS register. Signed-off-by: Matteo Fortini matteo.fort...@gmail.com --- arch/arm/mach-at91/include/mach/at91sam9_smc.h | 35 +-

[PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot

The configuration for NAND has been aligned with values from U-Boot and completed with TIMINGS initialization Signed-off-by: Matteo Fortini matteo.fort...@gmail.com --- arch/arm/boards/sama5d3xek/init.c | 31 +-- 1 file changed, 21 insertions(+), 10 deletions(-) diff

[PATCH V2] SAMA5D3 SMC: Fix CS offset and add TIMINGS register

As stated in section 29.19.35 of SAMA5D3 Series Datasheet, MODE register has offset 0x10 while at offset 0x0C there is a TIMINGS register. This patch series adds the register and configures it for sama5d3xek using timings from U-Boot [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add

[PATCH 0/3] MVEBU SoC ID and revision detection

This patch set adds support for reading SoC ID and revision from PCIe controllers found on Marvell MVEBU SoCs. Patch 1 adds PCI bus specific OF address translation required for reg property parsing of PCIe controller nodes. Patch 2 selects above PCI OF address translation for MVEBU SoCs. Patch

[PATCH 2/3] ARM: mvebu: select PCI specific DT bus translator

Marvell MVEBU DT files contain some nodes mapped to PCI address space, add the translator Kconfig to be able to iomap those node's addresses. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org --- arch/arm/Kconfig | 1 + 1 file changed, 1

[PATCH 1/3] drivers: of: import PCI bus specific translator

DT PCI address translation needs a special handling. This imports the corresponding translator into of/address.c but makes it selectable through Kconfig. Compared to the Linux version, we don't check for struct device_node's type which does not exist on Barebox but directly for device_type

[PATCH] i2c: omap: fix typo in dt_ids

Signed-off-by: Raphaël Poggi poggi.r...@gmail.com --- drivers/i2c/busses/i2c-omap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index f7108c2..adc952b 100644 --- a/drivers/i2c/busses/i2c-omap.c +++

Re: [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register

Hi Matteo, Thanks for your patch. Hi Jean-Christophe PLAGNIOL-VILLARD, For this patch series, can you give some comments (maybe the question from I need more discussion)? Thanks. On 06/24/2014 07:26 PM, Matteo Fortini wrote: As stated in section 29.19.35 of SAMA5D3 Series Datasheet, MODE