The three MX31 PLL may be clocked from either CKIH or a frequency-multiplied
derivate of CKIL generated by the Frequency Pre Multiplier FPM.
Add the pll_ref_clk selection infrastructure and support for MCU PLL bypass
to support clock switching and boards not clocked CKIH.
Signed-off-by: Alexander
On Mon, Jan 23, 2017 at 06:02:13PM +0100, Michael Olbrich wrote:
> A few small fixes to improve the barebox experience on EFI. Not all are
> strictly EFI specific, but that's where I came across the problems.
>
> Regards,
> Michael
>
> Michael Olbrich (5):
> readkey: keys are unsigned char
>
On Mon, Jan 23, 2017 at 10:01:04AM +0100, Yegor Yefremov wrote:
> I'm using dnsmaq as tftp server. When I execute tftp file on barebox
> 2016.07.0 I get the required file, but dnsmasq complains about missing
> ACK (my interpretation of dnsmaq source code). If I'm performing the
> same operation in
On Sun, Jan 22, 2017 at 09:57:35PM -0800, Andrey Smirnov wrote:
> Add driver for DSPI - SPI IP core found on various Freescale/NXP
> products (including Vybrid/VF610).
>
> Signed-off-by: Andrey Smirnov
> ---
> drivers/spi/Kconfig| 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/dspi_s
Hi Andrey,
On Sun, Jan 22, 2017 at 09:57:34PM -0800, Andrey Smirnov wrote:
> Add support for ZII VF610 Dev based designs such as:
>
> - VF610 Dev, revision B
> - VF610 Dev, revision C
> - CFU1, revision A
> - SPU3, revision A
> - SCU4 AIB, revision C
>
> Signed-off-by: Andrey
