Re: [PATCH v4 10/10] ARM: i.MX: Add support for ZII RDU1 board

Hi Andrey, On Wed, Jun 27, 2018 at 09:54:36PM -0700, Andrey Smirnov wrote: > +#include > +#include > +#include > +#include > +#include > + > +#define ZII_RDU1_DATAFLASH "/dev/dataflash0" > +#define ZII_RDU1_DATAFLASH_BAREBOX ZII_RDU1_DATAFLASH ".barebox" > + > +/** > + * zii_rdu1_

[PATCH 2/2] ARM: i.MX bbu: support partitions starting at i.MX header

The i.MX header is at an offset in the boot device, usually 0x400 bytes. This patch adds a flag to support the case that the partition the image is written to starts at that offset rather than 0x0. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx-bbu-internal.c | 7 +-- arch/arm/mach-im

[PATCH 1/2] ARM: i.MX bbu: reimplement IMX_INTERNAL_FLAG_KEEP_DOSPART flag

This patch reimplements the IMX_INTERNAL_FLAG_KEEP_DOSPART flag and makes it more generic. Until now we only kept a dos partition table over the update. Beginning with i.MX8 we may also want to preserve a GPT, so we have to extend the preserved area. It might also be the case that not (only) a par

Re: [PATCH v2 1/2] nvmem: Introduce nvmem_cell_get_and_read()

On Wed, Jun 27, 2018 at 09:42:26PM -0700, Andrey Smirnov wrote: > Introduce nvmem_cell_get_and_read() that combines getting a NVMEM cell > by name and reading its contents. > > Signed-off-by: Andrey Smirnov > --- > > Changes since [v1]: > > - Added missing newline to core.c Applied, thanks

Re: Troubles running qemu64 target

Guillaume: I haven't used QEMU ARM64 version of the code, but I have spent some time on i.MX8M which is ARM64 as well. See my comments below. On Thu, Jun 28, 2018 at 6:46 AM ranquet guillaume wrote: > > Hello. > > I'm pretty new to barebox and I'm having some troubles running the > qemu64 target

[PATCH] ARM: imx6qp: fix NoC QoS passthrough for new cpu type functions.

On i.MX6QP/DP cpu_mx6_is_mx6q/d do not return true anymore. Use the new cpu_mx6_is_mx6qp/dp to reenable NoC regulator bypass. Fixes: d4c05d29d484 ("ARM: i.MX6: Add cpu type for 'plus' variants") Signed-off-by: Philipp Zabel --- arch/arm/mach-imx/imx6.c | 3 +-- 1 file changed, 1 insertion(+), 2

Re: [PATCH] ARM: i.MX53: Set pll3 directly to 216MHz.

On Thu, Jun 28, 2018 at 10:30 AM, Sascha Hauer wrote: > On Wed, Jun 27, 2018 at 04:07:11PM +0200, Mogens Lauridsen wrote: >> PLL3 was first set to 400MHz and then some peripheral was switched >> to PLL3. Finally PLL3 was set to 216MHz. This could make some >> i.MX538 hang in a dead loop in the boo

Troubles running qemu64 target

Hello. I'm pretty new to barebox and I'm having some troubles running the qemu64 target. to top it off, I'm also new to the ARM world... and this is my first attempt at looking at a bootloader... I'm having trouble porting some hardware to barebox... and while I'm waiting for a JTAG probe, I thou

Re: [PATCH v2 1/2] nvmem: Introduce nvmem_cell_get_and_read()

Am Mittwoch, den 27.06.2018, 21:42 -0700 schrieb Andrey Smirnov: > Introduce nvmem_cell_get_and_read() that combines getting a NVMEM cell > by name and reading its contents. > > Signed-off-by: Andrey Smirnov For the series: Reviewed-by: Lucas Stach > --- > > Changes since [v1]: > > - Add

Re: [PATCH] ARM: i.MX53: Set pll3 directly to 216MHz.

On Wed, Jun 27, 2018 at 04:07:11PM +0200, Mogens Lauridsen wrote: > PLL3 was first set to 400MHz and then some peripheral was switched > to PLL3. Finally PLL3 was set to 216MHz. This could make some > i.MX538 hang in a dead loop in the boot process. Let's see what the code currently does: By rese

[PATCH v2 02/12] MIPS: Use generic GCC library routines from lib/

This is a port of Linux kernel commit | commit 740129b36faf049e6845819144542a0455e1e285 | Author: Antony Pavlov | Date: Wed Apr 11 08:50:19 2018 +0100 | | MIPS: Use generic GCC library routines from lib/ Signed-off-by: Antony Pavlov --- arch/mips/Kconfig | 3 +++ arch/mips/lib/Mak

[PATCH v2 08/12] RISC-V: erizo: enable nmon

Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f754aef05e..ff0d584761 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ choice config MACH_ERIZO bool "erizo fam

[PATCH v2 10/12] RISC-V: add erizo_generic_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/erizo_generic_defconfig | 53 ++ 1 file changed, 53 insertions(+) diff --git a/arch/riscv/configs/erizo_generic_defconfig b/arch/riscv/configs/erizo_generic_defconfig new file mode 100644 index 00..e62b6ec719 --- /d

[PATCH v2 07/12] RISC-V: erizo: add DEBUG_LL support

Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig| 1 + arch/riscv/mach-erizo/include/mach/debug_ll.h | 37 +++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d0e934e939..f754aef05e 100644 --- a/arch/ris

[PATCH v2 06/12] RISC-V: add nmon nano-monitor

nmon is a tiny (<1024 bytes) monitor program for the RV32I processors. It can operate with NO working RAM at all! It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging. Signed-off-by: Antony Pavlov ---

[PATCH v2 03/12] Add initial RISC-V architecture support

Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig | 62 +++ arch/riscv/Makefile | 72 ++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 + arch/riscv/boot/start.S

[PATCH v2 04/12] RISC-V: add Erizo SoC support

Erizo is an opensource hardware SoC for FPGA. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig | 11 ++ arch/riscv/Makefile| 3 ++ arch/riscv/boards/erizo-generic/.gitignore | 1 + arch/riscv/boards/erizo-generic/Makefile | 1 + arch/ri

[PATCH v2 11/12] scripts: add nmon-loader

Signed-off-by: Antony Pavlov --- scripts/nmon-loader | 31 +++ 1 file changed, 31 insertions(+) diff --git a/scripts/nmon-loader b/scripts/nmon-loader new file mode 100755 index 00..d80a53097a --- /dev/null +++ b/scripts/nmon-loader @@ -0,0 +1,31 @@ +#!/usr/bi

[PATCH v2 12/12] Documentation: add RISC-V docs

Signed-off-by: Antony Pavlov --- Documentation/boards/riscv.rst | 91 ++ 1 file changed, 91 insertions(+) diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst new file mode 100644 index 00..1a51d4d44f --- /dev/null +++ b/Documentati

[PATCH v2 01/12] lib: Add shared copies of some GCC library routines

This commit is based on these linux kernel commits: | commit b35cd9884fa5d81c9d5e7f57c9d03264ae2bd835 | Author: Palmer Dabbelt | Date: Tue May 23 10:28:26 2017 -0700 | | lib: Add shared copies of some GCC library routines | | commit e3d5980568fdf83c15a5a3c8ddca1590551ab7a2 | Author: Matt Re

[PATCH v2 05/12] RISC-V: add low-level debug macros for ns16550

This patch adds macros for ns16550 port initialization and single char output. The macros can be used in MIPS asm pbl code. Signed-off-by: Antony Pavlov --- arch/riscv/include/asm/debug_ll_ns16550.h | 186 ++ 1 file changed, 186 insertions(+) diff --git a/arch/riscv/include/

[PATCH v2 00/12] Add initial RISC-V architecture support

This patchseries adds initial RISC-V architecture support for barebox. See Documentation/boards/riscv.rst for instructions. You can obtain this patchseries from github: $ git clone -b 20180628.riscv https://github.com/frantony/barebox Changes since PATCH v1 (20170415) (http

[PATCH] ARM: i.MX53: Make clock tree setup better readable

Change write register accesses to read-modify-write accesses. This makes it clearer which bits are actually changed by the code. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/imx53.c | 27 +-- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/arch/arm/ma