Hi Sascha,
yes, unfortunately we have. We applied this just because we experienced
hangs in device booting tests. After this patch the NAND booting
problems went away. The booting failed during DMA page reading.
I just tested this again and after excluding the changes in this patch
the device
From: Steffen Trumtrar
Import the SoCFPGA bridges drivers from linux v4.10-rc2.
Description from the original commit:
e5f8efa5c8bf86c1fa698551d54db8f6aee221fd
ARM: socfpga: fpga bridge driver support
Supports Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
From: Steffen Trumtrar
Import the fpga bridge framework from linux v4.10-rc2.
Description from the initial commit adding this to linux:
21aeda950c5f84a8351b862816d832120b217a9b
fpga: add fpga bridge framework
This framework adds API functions for enabling/
disabling FPGA bridges
From: Steffen Trumtrar
Instead of defining the fpga-mgr structure in the socfpga driver, import
the fpga-mgr.h file from linux v4.13.
Signed-off-by: Steffen Trumtrar
---
drivers/firmware/socfpga.c | 9 +---
include/firmware.h | 1 +
include/fpga-mgr.h | 102
From: Steffen Trumtrar
Add support for potentially defined FPGA-bridges in the overlay.
While at it also add support for loading the firmware directly via a
path instead of 'needing' an overlay for that.
The direct loading will be done with the existent firmwareload command.
Signed-off-by:
From: Steffen Trumtrar
Since there is now a fpgamgr framework in barebox, the function names are
misleading. Change that to be SoCFPGA specific.
Signed-off-by: Steffen Trumtrar
---
drivers/firmware/socfpga.c | 58 +++---
1 file changed, 29 insertions(+), 29
From: Steffen Trumtrar
Description from the linux commit 5756e9dd0de6d5c307773f8f734c0684b3098fdd:
ARM: 6640/1: Thumb-2: Symbol manipulation macros for function body copying
In low-level board support code, there is sometimes a need to
copy a function body to another location at
From: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar
---
drivers/reset/core.c | 2 +-
include/linux/reset.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index 26a54f21df..1c9eeaec54 100644
--- a/drivers/reset/core.c
+++
From: Steffen Trumtrar
To make changes to the SDRAM controller effective, the APPLYCFG bit must
be set after programming the bitstream to the FPGA. This has to be done
without any SDRAM usage. Therefore copy the function to execute to the
OCRAM and execute it from there.
Signed-off-by: Steffen
From: Steffen Trumtrar
firmwareload can only load a bitstream into an FPGA without any
knowledge of possible additional needs (e.g. FPGA bridges).
These are defined in the fpga-region nodes in the devicetree. The
fpga-region describes the layout of the FPGA and the bridges it needs
en/disabled.
From: Steffen Trumtrar
The bridges are now handled via the bridges driver. There is no
need to hardcode the memory writes anymore.
Signed-off-by: Steffen Trumtrar
---
drivers/firmware/socfpga.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/firmware/socfpga.c
From: Sascha Hauer
When creating a 2nd level page table from a section inherit the flags
from the section rather than assuming the section was mapped cached
previously. This fixes creating a 2nd level pagetable when the section
was mapped differently than we expected.
Signed-off-by: Sascha
From: Steffen Trumtrar
At least bitstreams for FPGAs can consist of a lot of zeros depending on
device utilization. These bitstreams can be compressed very effectively.
Let the firmware code accept these images and decompress them before
handing it to the firmware-manager in question.
As of_firmware.c uses the firmwaremgr_load_file function, it depends on
FIRMWARE.
Signed-off-by: Steffen Trumtrar
---
drivers/of/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 23be25d85d..e58fe50f70 100644
--- a/drivers/of/Kconfig
+++
+Cc some Phytec guys
On Wed, Jan 20, 2021 at 01:52:03PM +0100, Andrej Picej wrote:
> Add support for automatic DRAM size detection on phytec phycard imx6q
> machines. Currently supported SoM variants are 1 GiB (1 bank) and 2 GiB
> variant. Machines now boot from internal SRAM (see DCD table
On Wed, Jan 20, 2021 at 01:51:07PM +0100, Andrej Picej wrote:
> During raw NAND booting, GPMI/BCH clock generation might fail due to
> improper clock gating conditions and consequently booting from NAND will
> fail. This is caused by silicon errata ERR007117. Apply errata fix
> workaround before
On Thu, Jan 21, 2021 at 07:56:58AM +0100, barebox+mail...@cookiesoft.de wrote:
> Hey Sasha,
>
> thanks for that patch, LGTM.
> I will integrate that into our yocto build system, should be fairly easy.
>
> Are you planning to patch that upstream?
Sure, I'll queue this for the next release.
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