On Wed, 05 May 2021 12:45:23 +0200
Jan Lübbe wrote:
> On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote:
> > LiteX is a Migen-based System on Chip, supporting softcore
> > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
> >
> > See https://github.com/enjoy-digital/litex and
> > https://gi
On Wed, 5 May 2021 12:39:14 +0200
Ahmad Fatoum wrote:
Hi Ahmad!
> Hello Antony,
>
> On 05.05.21 12:08, Antony Pavlov wrote:
> > Signed-off-by: Antony Pavlov
> > ---
> > drivers/spi/Kconfig | 3 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/litex_spiflash.c | 242 +
On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
>
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.
>
> Sig
Hello Antony,
On 05.05.21 12:08, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov
> ---
> drivers/spi/Kconfig | 3 +
> drivers/spi/Makefile | 1 +
> drivers/spi/litex_spiflash.c | 242 +++
> 3 files changed, 246 insertions(+)
>
> diff --gi
On Wed, 5 May 2021 12:19:02 +0200
Ahmad Fatoum wrote:
Hi Ahmad!
You are send your e-mails too fast, I can't keep up with you ;)
I see that your latest RISC-V changes are already in pengutronix next branch.
I'll try to take into account your notest and rebase my LiteX branch on top
of pengutro
On 05.05.21 12:08, Antony Pavlov wrote:
> This patch adds driver to support GPIO functionality
> for 74xx-compatible ICs with MMIO access.
>
> Compatible models include:
> 1 bit: 741G125 (Input), 741G74 (Output)
> 2 bits: 742G125 (Input), 7474 (Output)
> 4 bits: 74125 (Input)
On 05.05.21 12:08, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov
> ---
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_litex.c | 96 +++
> 2 files changed, 97 insertions(+)
>
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
On 05.05.21 12:08, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov
> ---
> arch/riscv/boards/erizo/lowlevel.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/boards/erizo/lowlevel.c
> b/arch/riscv/boards/erizo/lowlevel.c
> index d9edb530b7..185de6ed77 100644
> ---
Hello,
On 05.05.21 12:08, Antony Pavlov wrote:
> After migrating to PBL we can't use nmon assembler macro
> in C code anymore. Some changes are introduced to invoke
> nmon from PBL C code:
>
> * use 'lla' macro instruction instead of 'la';
> * don't touch the 'ra' register, use 'a2' instead;
Hello Antony,
On 05.05.21 12:18, Antony Pavlov wrote:
> On Tue, 27 Apr 2021 22:23:03 +0200
> Ahmad Fatoum wrote:
>
> Hi Ahmad!
>
> Could you please rebase this patchseries on top of pengutronix next branch
> and push it to github?
>
> My latest LiteX SoC support patchseries introduces
> mach-
Hello Antony,
On 05.05.21 12:08, Antony Pavlov wrote:
> Tested on Digilent Arty FPGA board.
>
> Signed-off-by: Antony Pavlov
> ---
> arch/riscv/boards/Makefile | 1 +
> arch/riscv/boards/litex-linux/Makefile | 3 +
> arch/riscv/boards/litex-linux/lowlevel.c | 20 +
> arch/
On Tue, 27 Apr 2021 22:23:03 +0200
Ahmad Fatoum wrote:
Hi Ahmad!
Could you please rebase this patchseries on top of pengutronix next branch
and push it to github?
My latest LiteX SoC support patchseries introduces
mach-litex/include/mach/debug_ll.h.
> With the recent changes, we can now delet
Hello Antony,
On 05.05.21 12:08, Antony Pavlov wrote:
> LiteX is a Migen-based System on Chip, supporting softcore
> VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
>
> See https://github.com/enjoy-digital/litex and
> https://github.com/litex-hub/linux-on-litex-vexriscv
> for details.
>
> Sign
LiteX is a Migen-based System on Chip, supporting softcore
VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.
Signed-off-by: Antony Pavlov
---
arch/riscv/Kconfig
Signed-off-by: Antony Pavlov
---
arch/riscv/configs/litex_linux_defconfig | 76
1 file changed, 76 insertions(+)
diff --git a/arch/riscv/configs/litex_linux_defconfig
b/arch/riscv/configs/litex_linux_defconfig
new file mode 100644
index 00..ab53df1c78
--- /dev/n
Tested on Digilent Arty FPGA board.
Signed-off-by: Antony Pavlov
---
arch/riscv/boards/Makefile | 1 +
arch/riscv/boards/litex-linux/Makefile | 3 +
arch/riscv/boards/litex-linux/lowlevel.c | 20 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/litex-linux.
Signed-off-by: Antony Pavlov
---
drivers/spi/Kconfig | 3 +
drivers/spi/Makefile | 1 +
drivers/spi/litex_spiflash.c | 242 +++
3 files changed, 246 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 323d93efeb..714d30e
LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM
Controll
This patch adds driver to support GPIO functionality
for 74xx-compatible ICs with MMIO access.
Compatible models include:
1 bit: 741G125 (Input), 741G74 (Output)
2 bits: 742G125 (Input), 7474 (Output)
4 bits: 74125 (Input), 74175 (Output)
6 bits: 74365 (Input), 74174 (Outp
After migrating to PBL we can't use nmon assembler macro
in C code anymore. Some changes are introduced to invoke
nmon from PBL C code:
* use 'lla' macro instruction instead of 'la';
* don't touch the 'ra' register, use 'a2' instead;
* add wrapper C function for nmon.
Signed-off-by: Antony
Signed-off-by: Antony Pavlov
---
drivers/serial/Makefile | 1 +
drivers/serial/serial_litex.c | 96 +++
2 files changed, 97 insertions(+)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7ff41cd5c7..95c3387d3e 100644
--- a/drivers/serial
Antony Pavlov (9):
RISC-V: make it possible to run nmon from PBL C code
RISC-V: boards: erizo: make it possible to use nmon
serial: add litex UART driver
gpio: add driver for 74xx-ICs with MMIO access
spi: add litex spiflash driver
net: add LiteEth driver
RISC-V: add initial LiteX SoC
Signed-off-by: Antony Pavlov
---
arch/riscv/boards/erizo/lowlevel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/boards/erizo/lowlevel.c
b/arch/riscv/boards/erizo/lowlevel.c
index d9edb530b7..185de6ed77 100644
--- a/arch/riscv/boards/erizo/lowlevel.c
+++ b/arch/riscv/boards/
Hey Lucas,
> Seems you imported this patch from somewhere and it left some traces in
> the commit message?
yes, sorry, my local mirror. I will fix that.
> Also I don't understand what this change is supposed to be doing. You
> are building just another Barebox binary, with no real differences in
Hello Michael,
Hello Lucas,
On 05.05.21 10:15, Lucas Stach wrote:
> Hi Michael,
>
> Am Montag, dem 03.05.2021 um 10:07 + schrieb Michael Graichen:
>> Since OCRAM is only 192K this introduces CONFIG_ZYNQ_BUILD_FSBL so we can
>> can chainload a more feature rich barebox via bootm.
>>
>> From 1
Hi Michael,
Am Montag, dem 03.05.2021 um 14:08 + schrieb Michael Graichen:
> This adds minimalistic support for USB on the Zedboard/Zynq-7000
This change does 3 distinct things and should be split in 3 patches to
do one thing at a time:
- add Zynq EHCI support
- add ULPI PHY ID
- add Zedboard
Hi Michael,
Am Montag, dem 03.05.2021 um 10:07 + schrieb Michael Graichen:
> Since OCRAM is only 192K this introduces CONFIG_ZYNQ_BUILD_FSBL so we can can
> chainload a more feature rich barebox via bootm.
>
> From 1f1a95eca42198d73c38cc12b9b44f061980cef8 Mon Sep 17 00:00:00 2001
> From: Mic
27 matches
Mail list logo
