Re: [PATCH] ddr: imx9: fix DRAM PLL bypass

On Fri, 18 Jul 2025 20:12:42 +0200, Mathieu Anquetin via B4 Relay wrote: > On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0 > of GPR_SHARED2 register. > > This is done using the generic function ccm_shared_gpr_set() which takes > two arguments, the GPR number and the value

Re: [PATCH] ddr: imx9: fix DRAM PLL bypass

Hi Mathieu, Thanks for your patch On 7/18/25 20:12, Mathieu Anquetin via B4 Relay wrote: > From: Mathieu Anquetin > > On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0 > of GPR_SHARED2 register. > > This is done using the generic function ccm_shared_gpr_set() which takes

RE: [PATCH] ddr: imx9: fix DRAM PLL bypass

. De : Mathieu Anquetin via B4 Relay Envoyé : vendredi 18 juillet 2025 20:12 À : Sascha Hauer; BAREBOX Cc : Fabian Pflug; Jonas Rebmann; ANQUETIN Mathieu Objet : [PATCH] ddr: imx9: fix DRAM PLL bypass From: Mathieu Anquetin On i.MX9, clock selection for DDR PHY is done by

[PATCH] ddr: imx9: fix DRAM PLL bypass

From: Mathieu Anquetin On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0 of GPR_SHARED2 register. This is done using the generic function ccm_shared_gpr_set() which takes two arguments, the GPR number and the value to set. However, this function did not use the GPR number t