[PATCH 15/21] MIPS: main_entry: properly set XTLB handler for 64-bit mode

[Denis Orlov]

The offset of the TLB Load exception is different when 64-bit addressing
is enabled - 0x80 is used instead of 0x0. To simplify things, just copy
the handler code twice, for each of the cases.

While at it, also remove the incomprehensible cpu_has_4kex check. All of
the supported CPUs have MIPS R4K compatible exception handling scheme
(and we even hardcode that), so what are we trying to achieve there
anyway?

Signed-off-by: Denis Orlov <denorl2...@gmail.com>
---
 arch/mips/boot/main_entry.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 99cd2ec846..237288a337 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -50,11 +50,9 @@ static void trap_init(void)
                set_except_vector(i, &handle_reserved);
        }
 
-       if (!cpu_has_4kex)
-               memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
-
        /* FIXME: handle tlb */
        memcpy((void *)(ebase), &except_vec3_generic, 0x80);
+       memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
        /* unset BOOT EXCEPTION VECTOR bit */
        write_c0_status(read_c0_status() & ~ST0_BEV);
-- 
2.41.0