Thanks, Kumar!
I ended up doing a slightly different program before reading your comment.
I used the STALL register to get how many clock cycles an instruction
spares, so that means the instruction actually takes 1 + stall. I came up
with these values for my BBB rev. A5A for the instructions tha
Sorry, just saw that you actually mentioned that the shared memory has the
same performance as the DRAM.
Also, I found
this:
http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit#Load_.2F_Store_Instructions
where it is said that LBBO should take (1+word count) cycles. If that's
rig
I was wrong about the number 1, actually after some experiments I noticed that
I'm still losing samples, even after setting the ACK_CLKDIV to something that
divides the 24MHz by 3. Anyway it is useful to know that you can obtain higher
sample rates by setting a lower value to that register.
I'd
Very nice findings!
Do you have a broader list of instructions and their duration?
And/or is there any official or unofficial documentation where these delays
could be taken from?
Also, you mentioned the PRU DRAM only - does it take the same time for the
shared memory?
Thanks a lot!
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It seems I was wrong, I noticed just the same amount of lost samples when
dividing the 24MHz by 1, 3 or 6.
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Dear Youngtae Jo, thanks for your kindness on sharing your code. It pushed
me to finally obtain some results.
However there are certain points that you need to take care on your code. I
will try to list at least most of them here:
1. you haven't set anything to the ADC_CLKDIV register. On my
Lenny, I'm sorry for this very late answer, but I found this topic really
useful and you guys have given me the right directions.
I got to check all the information you gave here in the SPRUH73 guide
(technical ashsssfyiafgygrf) and definitely, if one uses the default 3MHz
ADC clock or the CLK_M
