Board layout issue, crosstalk most likely
On Wednesday, November 16, 2016 at 3:06:31 AM UTC+2, Joe Phaneuf wrote:
>
> resolved, 100pF cap on SPI0 clock near the grove connector causing
> reflections, resulting in double-clocking data. sigh.
>
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The 100pF cap, C204, seems to me to be almost useless without a series bead
(or resistor) to divide down the EMI signal (2.4GHz).
That said, if UART2 pin is re-purposed as SPI_CLK, then I agree that C204
could be problematic.
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David McRell
On Saturday, December 3, 2016 at 7:28:30 AM UTC-6,
Thank you very much! I will try to remove it and see if any luck with the
spi0
On Sat, Dec 3, 2016 at 1:09 AM, Joe Phaneuf wrote:
> Pretty confident it's not kernel version. Actually explored that line of
> thinking a little, but there's a u-boot spi tool you can use to test before
> the ker
Pretty confident it's not kernel version. Actually explored that line of
thinking a little, but there's a u-boot spi tool you can use to test before
the kernel even loads, and you can replicate this issue with that.
FYI response from Seeed regarding the existence of the caps is that they're
for
Thanks! Could you tell me where is the cap on the board? Already read the
BBGW's SCH, but still couldn't figure it out
And do you think this is the problem caused by specific kernel versions
(I'm using ubuntu 16.04, 4.4.12-ti-r30)? I assume using SPI0 for
communication is really common among
Howdy, correct, had to completely remove the cap on the spi0 clock. Hope that
helps!
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Hey Joe,
spi0 on my BBGW also gave me the wrong result when I ran the spi test code
by shorting p18 and p21. How did you solve your problem? Replace the
cap
On Tuesday, November 15, 2016 at 6:58:35 AM UTC+8, Joe Phaneuf wrote:
>
> Hey, cross posting from seeed studio forums.
>
>
> tldr: cl
resolved, 100pF cap on SPI0 clock near the grove connector causing
reflections, resulting in double-clocking data. sigh.
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