[Beignet] [PATCH 4/8] BDW: Refine BDW's int 32*32 multiply.

BDW support int32 * int32 directly. So add a flag to selection for it. BDW use int32*int16 when use acc. Because int32*int16 also work in IVB, change to int32*int16 when use acc. Need refine int32*int32 to long later. Signed-off-by: Yang Rong --- backend/src/backend/gen8_context.cpp | 2 +

[Beignet] [PATCH 8/8] BDW: Correct scratch buffer of BDW.

BDW's scratch buffer change to power 2 alignment from 1024. Signed-off-by: Yang Rong --- backend/src/backend/gen8_context.cpp | 2 +- src/intel/intel_gpgpu.c | 22 ++ 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen8_contex

[Beignet] [PATCH 6/8] BDW: Add BDW Device id to gen binary generater and binary serialize in backend.

Signed-off-by: Yang Rong --- backend/src/backend/gen_program.cpp | 7 ++- backend/src/gbe_bin_generater.cpp | 4 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_program.cpp b/backend/src/backend/gen_program.cpp index 71a69dd..e94b9c0 100644 --- a

[Beignet] [PATCH 1/8] BDW: Fix Pointer argument curbe alloce size.

Because kernel will write 64bits address when reloc, so when reloc argument in the curbe bo, the pointer need 8 byte curbe. Signed-off-by: Yang Rong --- backend/src/backend/gen8_context.hpp | 2 ++ backend/src/backend/gen_context.cpp | 9 + backend/src/backend/gen_context.hpp | 2 ++ 3

[Beignet] [PATCH 7/8] BDW: Add device's sub slice field, for cl_get_kernel_max_wg_sz.

When SLM enable, get kernal max workgroup size should return the a sub slice's max thread * simdwidth. So need the sub slice information. Signed-off-by: Yang Rong --- src/cl_device_id.c | 13 +++-- src/cl_device_id.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git

[Beignet] [PATCH 2/8] BDW: enable SLM in BDW.

BDW's SLM control register change to L3CNTLREG, offset is 0x7034. Signed-off-by: Yang Rong --- src/intel/intel_defines.h | 2 ++ src/intel/intel_gpgpu.c | 51 +-- 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/src/intel/intel_defin

[Beignet] [PATCH 3/8] BDW: Fix unsample bug.

When set the hstride to 2, also need set vstride to 16. Signed-off-by: Yang Rong --- backend/src/backend/gen_encoder.cpp | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp index 6bb622

[Beignet] [PATCH 5/8] BDW: BDW don't need add slm offset, remove it.

Signed-off-by: Yang Rong --- backend/src/backend/gen8_context.cpp | 15 ++- backend/src/backend/gen_insn_selection.cpp | 1 - 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/backend/src/backend/gen8_context.cpp b/backend/src/backend/gen8_context.cpp index 72476

[Beignet] [PATCH 1/3] BDW: Pass Jip and Uip when patchJMPI.

Do not like GEN7, BDW's Jip is in bits4 and Uip is in bits3, so should set Jip and Uip independently. Signed-off-by: Yang Rong --- backend/src/backend/gen75_encoder.cpp | 14 ++ backend/src/backend/gen75_encoder.hpp | 2 +- backend/src/backend/gen8_encoder.cpp | 24

[Beignet] [PATCH 3/3] BDW: add some BDW function.

Add intel_gpgpu_load_vfe_state_gen8, intel_gpgpu_walker_gen8, intel_gpgpu_build_idrt_gen8. Reloc Dynamic State Base Address in gen7's intel_gpgpu_set_base_address, to unify intel_gpgpu_load_curbe_buffer and intel_gpgpu_load_idrt. Now can pass part of utest builtin_global_id. Signed-off-by: Yang

[Beignet] [PATCH 6/6] BDW: Add function intel_gpgpu_bind_buf for gen8.

From: Junyan He Must call cl_bind_buf instead of intel_gpgpu_bind_buf directly in intel_gpgpu. Signed-off-by: Junyan He --- src/intel/intel_gpgpu.c | 36 +++- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/src/intel/intel_gpgpu.c b/src/intel/inte

[Beignet] [PATCH 2/3] BDW: Refine intel_gpgpu_setup_bti and add intel_gpgpu_set_base_address for BDW.

Because the sizeof struct surface state change in BDW, remove gen6_surface_state, and use gen_surface_state as the unoin of gen7_surface_state and gen8_surface_state. Use gen_surface_state in surface_heap_t. Reloc the Dynamic State Base and Instruction Address in intel_gpgpu_set_base_address_gen8

[Beignet] [PATCH 2/5] BDW: Add BDW pci ids and BDW device struct.

Signed-off-by: Yang Rong --- src/cl_device_data.h | 42 +- src/cl_device_id.c | 98 ++-- 2 files changed, 136 insertions(+), 4 deletions(-) diff --git a/src/cl_device_data.h b/src/cl_device_data.h index 28bd5f0..29827aa 100644

[Beignet] [PATCH 5/6] BDW: Correct surface base address set in setup bti.

From: Junyan He Signed-off-by: Junyan He --- src/intel/intel_gpgpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 63d44e7..6b8fa38 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -815,15 +

[Beignet] [PATCH 2/6] BDW: Add gen8 surface state struct.

From: Junyan He Signed-off-by: Junyan He --- src/intel/intel_structs.h | 161 ++ 1 file changed, 161 insertions(+) diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h index ef76bb4..cbda90e 100644 --- a/src/intel/intel_structs.h +++ b/

[Beignet] [PATCH 3/6] BDW: refine the gen8_surface_state_t.

From: Junyan He Signed-off-by: Junyan He --- src/intel/intel_structs.h | 118 +++--- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h index cbda90e..415df8d 100644 --- a/src/intel/intel_

[Beignet] [PATCH 4/6] BDW: Add function intel_gpgpu_setup_bti for gen8.

From: Junyan He Also set the correct surface cache control. Signed-off-by: Junyan He --- src/cl_driver.h | 16 src/intel/intel_gpgpu.c | 39 +++ 2 files changed, 55 insertions(+) diff --git a/src/cl_driver.h b/src/cl_driver.h index

[Beignet] [PATCH 1/6] BDW: Add gen8 into intel_driver_init

From: Junyan He Signed-off-by: Junyan He --- src/cl_command_queue.c | 2 +- src/intel/intel_driver.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/cl_command_queue.c b/src/cl_command_queue.c index 4cbb4eb..48deba0 100644 --- a/src/cl_command_queue.c +++ b/src/cl

[Beignet] [PATCH 1/5] Avoid use GenNativeInstruction directly out of GenEncode and gen_insn_compact.

Use the void* instead of when do instruction compact/decompact. Signed-off-by: Yang Rong --- backend/src/backend/gen_context.cpp | 2 +- backend/src/backend/gen_insn_compact.cpp | 3 ++- backend/src/backend/gen_program.cpp | 6 +++--- backend/src/backend/gen_program.hpp | 2 +- 4

[Beignet] [PATCH 4/5] BDW: Add Gen8Encoder and Gen7Encoder.

Class Gen8Encoder and Gen7Encoder derive from GenEncoder, and Gen75Encoder derive from Gen7Encode. GenNativeInstruction is handled in class GenEncoder, Gen7NativeInstruction is handled in class Gen7Encoder and Gen75Encoder, and Gen8NativeInstruction is handled in classe Gen8Encoder. Disable Gen8

[Beignet] [PATCH 5/5] BDW: Add class Gen8Context.

Now Gen8Context is almost same as Gen75Context, but still derive Gen8Context from GenContext for clearly. Signed-off-by: Yang Rong --- backend/src/CMakeLists.txt | 2 + backend/src/backend/gen8_context.cpp | 113 +++ backend/src/backend/gen8_context.h

[Beignet] [PATCH 3/5] BDW: Add BDW instruction define.

Seperate GEN7 instruction and GEN8 instrunction. GenNativeInstruction will become a union of Gen7NativeInstruction and Gen8NativeInstruction. Signed-off-by: Yang Rong --- backend/src/backend/gen7_instruction.hpp | 525 ++ backend/src/backend/gen8_instruction.hpp | 52

Re: [Beignet] About Intel Core M (aka Broadwell) support and OCL 2.0 roadmap..

Hi, You can expect BDW support in our next release at the end of this year. And OpenCL 2.0 support in 2015. Thanks Zou Nanhai From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of oscar bg Sent: Monday, September 29, 2014 12:32 PM To: beignet@lists.freedeskt

[Beignet] About Intel Core M (aka Broadwell) support and OCL 2.0 roadmap..

Hi, I mailed to this list more than a year ago just before Haswell launch asking for support for it.. now in 2014 seems we have this support with 1.2 support.. In that mail also was answered that Broadwell support was scheduled for 2014.. now with Intel Core M processors coming in a few days (next