Re: [Beignet] [PATCH v2 2/4] Add extensions intel_accelerator and basic intel_motion_estimation.

yes, we should remove assert here. We have finished error check for CL_INVALID_IMAGE_FORMAT somewhere. As for CL_INVALID_IMAGE_SIZE, actually the spec does not list any specific requirement for the image size, I talked with the extension contact, he thought it is reasonable to remove it. We

Re: [Beignet] [PATCH] remove register name which is no longer there

This patch LGTM, and my patchset includes this change. I will rebase after both of them got reviewed. Thanks. On Mon, Sep 14, 2015 at 06:56:37AM +0800, Guo Yejun wrote: > 8b9672ae40 removed the register laneid and should remove the name > at same patch, but missed. > > Signed-off-by: Guo Yejun

Re: [Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

Please ignore this patch, it seems there are some issues after this change. I will look into it and send it again when things got fixed. Thanks, Zhigang Gong. On Mon, Sep 14, 2015 at 02:19:36PM +0800, Zhigang Gong wrote: > Signed-off-by: Zhigang Gong > --- >

[Beignet] [PATCH 2/5] GBE: refine longjmp checking.

Signed-off-by: Zhigang Gong --- backend/src/backend/gen_insn_selection.cpp | 2 +- backend/src/ir/function.hpp| 17 + 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_insn_selection.cpp

[Beignet] [PATCH 4/5] GBE: don't always allocate ir::ocl::one/zero

Use liveness information, we can only allocate them on demand. And they could be treated as non-curbe-payload register. Signed-off-by: Zhigang Gong --- backend/src/backend/gen_context.cpp| 10 -- backend/src/backend/gen_reg_allocation.cpp | 12

[Beignet] [PATCH 3/5] GBE: don't treat btiUtil as a curbe payload register.

Btiutil should be just a normal temporary register and only alive for those specific laod/store instructions with mixed BTI used. Although btiutil only takes one DW register space, but in practice, it may waste one entire 32-byte register space as it has very long live range. This patch fix this

[Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

Signed-off-by: Zhigang Gong --- backend/src/backend/context.hpp| 2 +- backend/src/backend/gen_reg_allocation.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/backend/src/backend/context.hpp b/backend/src/backend/context.hpp index

[Beignet] [PATCH 1/5] GBE: refactor curbe register allocation.

The major motivation is to normalize the curbe payload's allocation and prepare to use liveness information to avoid unecessary payload register allocation and avoid fragments when allocate curbe registers. For an example, for GBE_CURBE_LOCAL_ID_Y/Z, many one dimention kernels don't need them. But

[Beignet] [PATCH 0/5] curbe register allocation refactor and optimization

This patch series is to fix the hacky curbe register allocation. Before, we treat these registers totally different way to the other normal registers. Then we do a lot of patch work in the backend stage to handle curbe register firstly and even before interval computing, thus we have to allocate

Re: [Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

It turns out that the issue was not caused by this patch, so this patch is good to go. I already submitted another patch to fix that liveness bug. Thanks, Zhigang Gong. > -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of > Zhigang Gong >

[Beignet] [PATCH] GBE: fix a zero/one's liveness bug.

This is a long standing bug, and is exposed by my latest register allocation refinement patchset. ir::ocl::zero and ir::ocl::one are global registers, we have to compute its liveness information carefully, not just get a local interval ID. Signed-off-by: Zhigang Gong ---