Re: [Beignet] [PATCH v3 3/3] add utest for creating 2d image from buffer.

2 comments inline, thanks. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of xionghu@intel.com Sent: Wednesday, September 09, 2015 1:44 PM To: beignet@lists.freedesktop.org Cc: Luo, Xionghu Subject: [Beignet] [PATCH v3 3/3] add utest for

[Beignet] [PATCH] GBE: implement pre-register-allocation instruction scheduling.

To find out an instruction scheduling policy to achieve the theoretical minimum registers required in a basic block is a NP problem. We have to use some heuristic factor to simplify the algorithm. There are many researchs which indicate a bottom-up list scheduling is much better than the top-down

[Beignet] [PATCH 2/8] Backend: Add FDIV64 function for gen_insn_selection.

From: Junyan He Signed-off-by: Junyan He --- backend/src/backend/gen_context.cpp| 4 +++ backend/src/backend/gen_context.hpp| 1 + .../src/backend/gen_insn_gen7_schedule_info.hxx| 1 +

[Beignet] [PATCH 0/8] Implement double division on BDW

From: Junyan He We use the macro: r0 = 0, r6 = a, r7 = b, r1 = 1 math.eo.f0.0 (4) r8.acc2 r6.noacc r7.noacc 0xE (-f0.0) if madm (4) r9.acc3 r0.noacc r6.noacc r8.acc2 // Step(1), q0=a*y0 madm (4) r10.acc4 r1.noacc -r7.noacc r8.acc2 // Step(2), e0=(1-b*y0)

[Beignet] [PATCH 4/8] Backend: Add MATH_WITH_ACC function.

From: Junyan He Also add setSrc0WithAcc and setSrc1WithAcc help functions to set the correct special accumulator fields of instruction. Signed-off-by: Junyan He --- backend/src/backend/gen8_encoder.cpp | 61

[Beignet] [PATCH 5/8] Backend: Add the MADM function to gen8 encoder.

From: Junyan He Signed-off-by: Junyan He --- backend/src/backend/gen8_encoder.cpp | 56 backend/src/backend/gen8_encoder.hpp | 2 ++ backend/src/backend/gen_defs.hpp | 2 ++ 3 files changed, 60

[Beignet] [PATCH 3/8] Backend: Add gen8 instruction field for special accumulator.

From: Junyan He The madm and invm function need to set accumulator id in the instruction. On BDW, the write mask of the dst and channel mask of src are reinterpreted for acc2~acc9 selection. Signed-off-by: Junyan He ---

[Beignet] [PATCH 8/8] Utest: Add double division test.

From: Junyan He Signed-off-by: Junyan He --- kernels/compiler_double_4.cl | 5 - kernels/compiler_double_div.cl | 5 + utests/CMakeLists.txt | 1 + utests/compiler_double_4.cpp | 40

[Beignet] [PATCH 7/8] Backend: Add madm and invm instrucions to disasm.

From: Junyan He We also add special accumulator field print to disasm. Signed-off-by: Junyan He --- backend/src/backend/gen/gen_mesa_disasm.c | 89 +-- 1 file changed, 84 insertions(+), 5 deletions(-) diff

[Beignet] [PATCH 6/8] Backend: Implement FDIV64 on BDW.

From: Junyan He According to the document, we use a set of instructions to implement double type division. Signed-off-by: Junyan He --- backend/src/backend/gen8_context.cpp | 68

Re: [Beignet] [PATCH 6/8] Backend: Implement FDIV64 on BDW.

On Tue, Sep 15, 2015 at 06:00:57AM -0700, Matt Turner wrote: > Date: Tue, 15 Sep 2015 06:00:57 -0700 > From: Matt Turner > To: "junyan.he" > Cc: "beignet@lists.freedesktop.org" > Subject: Re: [Beignet] [PATCH 6/8] Backend:

Re: [Beignet] [PATCH 5/8] Backend: Add the MADM function to gen8 encoder.

On Tue, Sep 15, 2015 at 05:57:13AM -0700, Matt Turner wrote: > Date: Tue, 15 Sep 2015 05:57:13 -0700 > From: Matt Turner > To: "junyan.he" > Cc: "beignet@lists.freedesktop.org" > Subject: Re: [Beignet] [PATCH 5/8] Backend:

Re: [Beignet] [PATCH 3/8] Backend: Add gen8 instruction field for special accumulator.

On Tue, Sep 15, 2015 at 4:15 AM, wrote: > From: Junyan He > > The madm and invm function need to set accumulator id in the > instruction. On BDW, the write mask of the dst and channel > mask of src are reinterpreted for acc2~acc9 selection. > >

Re: [Beignet] [PATCH 5/8] Backend: Add the MADM function to gen8 encoder.

On Tue, Sep 15, 2015 at 4:15 AM, wrote: > From: Junyan He > > Signed-off-by: Junyan He > --- > backend/src/backend/gen8_encoder.cpp | 56 > > backend/src/backend/gen8_encoder.hpp |

Re: [Beignet] [PATCH 6/8] Backend: Implement FDIV64 on BDW.

On Tue, Sep 15, 2015 at 4:15 AM, wrote: > From: Junyan He > > According to the document, we use a set of instructions > to implement double type division. > > Signed-off-by: Junyan He > --- >