Re: [Beignet] cl_intel_subgroups support

Hi Andrew, The block read/write extension patches have all been sent. Please visit https://patchwork.freedesktop.org/project/beignet/patches/ or mail-list for them. If you have face any problem, please feedback that we can fix the bugs. Thanks Xiuli From: Beignet

[Beignet] [PATCH] Runtime: Disable image hostptr for default

From: Pan Xiuli Image with hostptr can not use tiling and can be very slow when need access image. Disable image hostptr for default for good profermance. Add an option OCL_IMAGE_HOSTPTR to enable ture image hostptr. Signed-off-by: Pan Xiuli ---

[Beignet] [PATCH 3/4] Backend: Add intel_sub_group_shuffle_down/up/xor

From: Pan Xiuli Using a function shuffle delta for down/up, using some flags for current and down/up src switch. The flags and index is pre caculated in libocl. The shuffle delta only handle flag mask the dst with different src. Using the old shuffle with xor for

[Beignet] [PATCH 4/4] Utest: Add test case for sub_group_shuffle_down/up/xor

From: Pan Xiuli Signed-off-by: Pan Xiuli --- kernels/compiler_sub_group_shuffle_down.cl | 19 kernels/compiler_sub_group_shuffle_up.cl | 19 kernels/compiler_sub_group_shuffle_xor.cl | 19 utests/CMakeLists.txt

[Beignet] [PATCH 1/4] Backend: Add missing math function control code for gen8+

From: Pan Xiuli Signed-off-by: Pan Xiuli --- backend/src/backend/gen/gen_mesa_disasm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c index 9955dfc..5653275

[Beignet] [PATCH 2/4] Backend: Refine sel ir optimization

From: Pan Xiuli We may have some inst like: mov %30, %3 (-f0.1) mov %30, %4 (+f0.1) mov %30, %5 to mask some value out with the flag. Now only the last mov will left after optimization. This patch add check about if the intemedia can be replaced even if they are in