Signed-off-by: Guo, Yejun
---
src/cl_mem.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/cl_mem.c b/src/cl_mem.c
index 2b783b9..6a4729d 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -801,9 +801,10 @@ void* cl_mem_svm_allocate(cl_context ctx, cl_svm_mem_flags
flag
please hold on my v2 patch.
let me first try to refine code starting from GenEncoder::setMessageDescriptor.
-Original Message-
From: Song, Ruiling
Sent: Thursday, November 24, 2016 8:15 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH 2/4] support sends (sp
> -Original Message-
> From: Guo, Yejun
> Sent: Thursday, November 24, 2016 10:55 AM
> To: Song, Ruiling ; beignet@lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH 2/4] support sends (split send) for untyped
> write
>
> > + unsigned
> > Gen9Encoder::setUntypedWriteSendsMessageDesc
From: Pan Xiuli
We may need some bigger family like OWORD or HWORD and 32 word will be a
reg. This can be used for tmp and header registers.
Signed-off-by: Pan Xiuli
---
backend/src/backend/gen_reg_allocation.cpp | 8 ++--
backend/src/ir/register.cpp| 3 +++
backend/src/ir/
From: Pan Xiuli
We now can have a one reg size register using FAMILY_REG, refine the
header and tmp to be one reg size.
Signed-off-by: Pan Xiuli
---
backend/src/backend/gen_insn_selection.cpp | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/backend/src/backe
