On Wed, May 17, 2017 at 1:20 AM, rander.wang wrote:
> LLVM transform Mad(a, -b, c) to
> Add b, -b, 0
> Mad val, a, b, c
I think you mean that LLVM translates
> Add b, -b, 0
> Mad val, a, b, c
to
> Mad(a, -b, c)
As it is
In the patch title and the code: negtive -> negative
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On Wed, Apr 27, 2016 at 12:43 AM, Ruiling Song wrote:
> v2:
> fix build error.
Some documentation or description about this would be very welcome. I
cannot honestly imagine anyone being able to review this without it,
and I think I know what this patch is doing. :)
Some
On Wed, Oct 21, 2015 at 8:21 PM, Pan Xiuli wrote:
> Add a testcase for compiler mix. Since mix will have
> error, we take err limit as 1e-3 and print the max err.
I don't know what OpenCL's spec says about this issue, but you should
be aware that Gen's LRP instruction does
On Tue, Sep 15, 2015 at 4:15 AM, wrote:
> From: Junyan He
>
> The madm and invm function need to set accumulator id in the
> instruction. On BDW, the write mask of the dst and channel
> mask of src are reinterpreted for acc2~acc9 selection.
>
>
On Tue, Sep 15, 2015 at 4:15 AM, wrote:
> From: Junyan He
>
> Signed-off-by: Junyan He
> ---
> backend/src/backend/gen8_encoder.cpp | 56
>
> backend/src/backend/gen8_encoder.hpp |
On Tue, Sep 15, 2015 at 4:15 AM, wrote:
> From: Junyan He
>
> According to the document, we use a set of instructions
> to implement double type division.
>
> Signed-off-by: Junyan He
> ---
>
On Thu, Aug 6, 2015 at 12:57 AM, xionghu@intel.com wrote:
From: Luo Xionghu xionghu@intel.com
should define and use M_180_PI_F directly instead of using 180/M_PI_F.
Signed-off-by: Luo Xionghu xionghu@intel.com
---
backend/src/libocl/include/ocl_float.h | 1 +
On Thu, May 21, 2015 at 1:25 AM, junyan...@inbox.com wrote:
From: Junyan He junyan...@linux.intel.com
Because the CPU of X86 does not support half float
instructions, there is no support for half float operations.
So we introduce the half class to handle the operations for
half float using
On Thu, May 21, 2015 at 1:25 AM, junyan...@inbox.com wrote:
From: Junyan He junyan...@linux.intel.com
Signed-off-by: Junyan He junyan...@linux.intel.com
---
backend/src/backend/gen/gen_mesa_disasm.c | 83
+--
1 file changed, 78 insertions(+), 5 deletions(-)
On Mon, Mar 9, 2015 at 10:59 PM, xionghu@intel.com wrote:
From: Luo Xionghu xionghu@intel.com
translate native mad to llvm.fma.
I'm not sure that it matters for this patch, but do we know if Gen's
MAD instruction is a fused-multiply-add? That is, does it not do an
intermediate
On Tue, Mar 10, 2015 at 2:19 AM, Zhigang Gong
zhigang.g...@linux.intel.com wrote:
2. The double support is not fully supported. For example, all the math
functions and even the divide instruction is not supported.
You're right that the hardware doesn't natively do most of the math
operations
On Tue, Mar 10, 2015 at 6:55 PM, Song, Ruiling ruiling.s...@intel.com wrote:
I'm not sure that it matters for this patch, but do we know if Gen's MAD
instruction is a fused-multiply-add? That is, does it not do an intermediate
rounding step after the multiply?
I also have such kind of concern,
On Wed, Jan 28, 2015 at 11:18 PM, Ruiling Song ruiling.s...@intel.com wrote:
Avoid if-branching.
Signed-off-by: Ruiling Song ruiling.s...@intel.com
---
backend/src/libocl/tmpl/ocl_common.tmpl.cl | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git
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