Re: [Beignet] [PATCH] CMAKE: Use DRM_INTEL_LIBDIR for CHECK_LIBRARY_EXISTS path

This patch LGTM, thanks. On Thu, Jun 30, 2016 at 2:48 PM, Xiuli Pan wrote: > From: Pan Xiuli > > We check libdrm-intel with pkg-config, but CHECK_LIBRARY_EXISTS may > search lib in different path, so add the path we will use for it. > > Signed-off-by:

[Beignet] [PATCH 2/2] update android version.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- src/Android.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Android.mk b/src/Android.mk index 3d9102e..9b63f7e 100644 --- a/src/Android.mk +++ b/src/Android.mk @@ -7,7 +7,7 @@ include $(LOCA

[Beignet] [PATCH 1/2] Remove nonexisting unit test cases in Android.mk.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- utests/Android.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/utests/Android.mk b/utests/Android.mk index 963b698..63dba2a 100644 --- a/utests/Android.mk +++ b/utests/Android.mk @@ -175,8 +175,6 @@ LOCAL_SRC

Re: [Beignet] [PATCH] GBE: Optimize extraLiveOut register info.

This patch LGTM, thx. On Thu, Jun 2, 2016 at 10:21 AM, Ruiling Song wrote: > extraLiveout anlysis is used to detect registers defined in loop and > used out-of the loop. Previous logic may also include registers defined > BEFORE loop and live-through loop as

Re: [Beignet] [Patch V2 07/10] GBE: disable the read byte as DW.

The whole patchset LGTM, thanks. On Thu, May 26, 2016 at 12:24 PM, Yang Rong <rong.r.y...@intel.com> wrote: > From: Zhigang Gong <zhigang.g...@intel.com> > > Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> > --- > backend/src/backend/gen_insn_selectio

[Beignet] [PATCH] Refine custom unrolling policy.

We should use the production of current trip count and parent trip count to determine whether we should unroll the parent loop. Signed-off-by: Zhigang Gong <zhigang.g...@linux.intel.com> --- backend/src/llvm/llvm_unroll.cpp | 21 - 1 file changed, 12 insertions

[Beignet] [PATCH] Revert "GBE: disable mad for some cases."

This reverts commit d73170df3508d18e250d0af118e3b7955401194f. Actually, MAD should be always faster if we can use it to replace orignal Multiply + ADD. So let's revert this patch. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_insn_selection.cp

Re: [Beignet] [PATCH] Runtime: because double's built-ins haven't completely support, so disable it by default.

This patch LGTM. Thanks, Zhigang Gong. > -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of > Yang Rong > Sent: Tuesday, December 22, 2015 4:37 PM > To: beignet@lists.freedesktop.org > Cc: Yang Rong <rong.r.y...@intel.com

Re: [Beignet] [PATCH] runtime: silent some error messages.

use something like DEBUG_PRINT is better. Need to cleanup the whole library to fix this type of things. Thanks, Zhigang Gong On Tue, Nov 17, 2015 at 10:11 AM, Song, Ruiling <ruiling.s...@intel.com> wrote: > Hi Zhigang, > > Directly remove the output message may be not prope

[Beignet] [PATCH 2/5] GBE: don't assert even if we fail to compile kernel at the backend stage.

We should not assert even if the application triggers a internal limitation such as lack of scratch space. We should return error to the application and let the application to make further decision. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/conte

[Beignet] [PATCH 4/5] runtime: set CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE to kernel's SIMD_WIDTH.

It makes sense to set CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE to the corresponding SIMD size. Then it provides a way for intel's OCL application to get SIMD width at runtime and make some SIMD width dependant optimization possible. Signed-off-by: Zhigang Gong <zhigang.g...@intel.

[Beignet] [PATCH 3/5] GBE: remove useless assertions code.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.cpp | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/backend/src/backend/context.cpp b/backend/src/backend/context.cpp index 47d8a45..5f5a858 100644 --- a/backend/src/b

[Beignet] [PATCH 1/5] GBE: extent register allocator size/offset to 32bit.

Because the range of scratch size exceed the int16_t's maximum size. We have to extent these elements to 32 bit. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.cpp | 52 - backend/src/backend/context.hpp | 6 ++

[Beignet] [PATCH 5/5] GBE: decrease the loop unrolling threshold to 640.

1024 is some how too large for some kernels and may cause some kernels fail to build due to lack of enough scratching space. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/llvm/llvm_to_gen.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backe

[Beignet] [PATCH] runtime: silent some error messages.

We already set corresponding error code and return it to the caller. Don't bother to print the error messages in beignet internal. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- src/cl_command_queue_gen7.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cl_command_queu

Re: [Beignet] [PATCH 4/4] runtime: dynamically get global memory size and max alloc size

LGTM, thx. On Wed, Oct 14, 2015 at 04:34:07PM +0800, Pan Xiuli wrote: > Now device and driver can support bigger memory, we need to abandon > our old 2G hard code. We get global memory by considering device > limitation, drm driver and kernel support and raw, this will ensure > a bigger global

Re: [Beignet] [PATCH 1/4] drivers: change the buf size to size_t

On Wed, Oct 14, 2015 at 04:34:04PM +0800, Pan Xiuli wrote: > The uint32_t size is not enough for coming bigger > gpu memory, now GEN9 support 4G buffer. Also add > assertion for invalid size. > > Signed-off-by: Pan Xiuli > --- > src/cl_driver.h | 2 +- >

Re: [Beignet] [PATCH 2/4] runtime: refine the cl_device_id to support bigger memory

This patch LGTM, thx. On Wed, Oct 14, 2015 at 04:34:05PM +0800, Pan Xiuli wrote: > Now gen8 and gen9 support 4G global memory, and gen9 support > 4G single buffer. Need to move the global_mem and max_mem_alloc > size into each define header. > > Signed-off-by: Pan Xiuli >

Re: [Beignet] [PATCH 3/4] driver: add setup_bti_gen9 for bigger buffer up to 4G

On Wed, Oct 14, 2015 at 04:34:06PM +0800, Pan Xiuli wrote: > Now gen9 can support bigger buffer size, and it can also support > 4G global memory. We add new function to support it. > > Signed-off-by: Pan Xiuli > --- > src/intel/intel_gpgpu.c | 41

Re: [Beignet] [PATCH] driver/runtime: get global mem size dynamically

, please be aware if the test machine has only 4GB memory, it will never hit the GPU memory space above 2GB. Thanks, Zhigang Gong. On Fri, Oct 09, 2015 at 08:56:38AM +, Pan, Xiuli wrote: > So I have rewrite the code here, and I think we should not using totalgpumem > for max_mem_allo

[Beignet] [PATCH] GBE: fix kernel arguments uploading bug.

-off-by: Zhigang Gong <zhigang.g...@intel.com> --- src/cl_command_queue_gen7.c | 6 -- src/cl_kernel.c | 8 +--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/cl_command_queue_gen7.c b/src/cl_command_queue_gen7.c index 8c09615..2edc3be 100644 ---

Re: [Beignet] [PATCH] driver/runtime: get global mem size dynamically

ts the maximum memory size, and there are some aperture space already allocated by system, then the case may be failed. Before submit the patch, it's better to test it with all the related conformance test cases on all platforms. Or maybe we need to add some cases to test edge conditions int

Re: [Beignet] [PATCH 3/4] Fix a event leak in create context

Nice catch, this patch LGTM. On Thu, Sep 24, 2015 at 05:13:26PM +0800, Pan Xiuli wrote: > We get an event out of NDRangeKernel, and we don't release it. > As an gpgpu event it can also make drm buffer leak, to avoid > potenial error we just release it.w > > Signed-off-by: Pan Xiuli

Re: [Beignet] [PATCH] GBE: fix a zero/one's liveness bug.

Ping for review. On Tue, Sep 22, 2015 at 03:45:29PM +0800, Zhigang Gong wrote: > Ping for review. > Thanks. > > On Mon, Sep 14, 2015 at 03:50:00PM +0800, Zhigang Gong wrote: > > This is a long standing bug, and is exposed by my latest register > > allocation refinement

Re: [Beignet] [PATCH V2 3/3] add local copy propagation optimization for each basic block

On Thu, Sep 24, 2015 at 06:05:31AM +, Guo, Yejun wrote: > > > -Original Message- > From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com] > Sent: Thursday, September 24, 2015 12:32 PM > To: Guo, Yejun > Cc: beignet@lists.freedesktop.org > Subject: Re: [Bei

Re: [Beignet] [PATCH V2] GBE: Implement liveness dump.

LGTM. On Thu, Sep 24, 2015 at 03:47:30PM +0800, Ruiling Song wrote: > v2: > remove old printf debug code. > Signed-off-by: Ruiling Song > --- > backend/src/ir/liveness.cpp | 58 > - > 1 file changed, 20 insertions(+), 38

[Beignet] [Patch v2] GBE: refine longjmp checking.

v2: simplify the logic in function.hpp. Let the user to prepare correct start and end point. Fix the incorrect start/end point for one forward jump and one backward jump case. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_insn_selection.cp

Re: [Beignet] [PATCH] GBE: Implement liveness dump.

LGTM, and you can remove those useless printf code now. On Thu, Sep 24, 2015 at 10:05:07AM +0800, Ruiling Song wrote: > Signed-off-by: Ruiling Song > --- > backend/src/ir/liveness.cpp | 20 > 1 file changed, 20 insertions(+) > > diff --git

Re: [Beignet] [PATCH V2 3/3] add local copy propagation optimization for each basic block

On Thu, Sep 24, 2015 at 02:58:22AM +, Guo, Yejun wrote: > > > -Original Message- > From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com] > Sent: Thursday, September 24, 2015 9:14 AM > To: Guo, Yejun > Cc: beignet@lists.freedesktop.org > Subject: Re: [Bei

[Beignet] [Patch v2] GBE: Don't try to remove instructions when liveness is in dynamic update phase.

incorrect liveness checking for special registers. Now remove them. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/llvm/llvm_gen_backend.cpp | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/backend/src/llvm/llvm_gen_backend.

[Beignet] [PATCH 6/9] GBE: continue to refine interfering check.

of interleve check functions of DAG class. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 133 --- backend/src/ir/value.hpp | 13 +++-- 2 files changed, 123 insertions(+), 23 deletions(-) diff --git a/backend/

[Beignet] [PATCH 4/9] GBE: add some dag helper routines to check registers' interfering.

These helper function will be used in further phi mov optimization. v2: remove the useless debug message code. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 100 +++ backend/src/ir/value.hpp | 13 ++ 2

[Beignet] [PATCH 2/9] GBE: refine liveness analysis.

Only in gen backend stage, we need to take care of the special extra liveout and uniform analysis. In IR stage, we don't need to handle them. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.cpp | 2 +- backend/src/ir/liveness.cpp

[Beignet] [PATCH 3/9] GBE: add two helper routines for liveness partially update.

We don't need to recompute the entire liveness information for all cases. This is a preparation patch for further phi copy optimization. v2: also need to update varKill set. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/liveness.cp

[Beignet] [PATCH 9/9] GBE: avoid vector registers when there is high register pressure.

let's simply avoid use vector registers and just use a temporary short-live-interval vector. v2: remove out-of-date comments. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_reg_allocation.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff

[Beignet] [PATCH 1/9] GBE: refine Phi copy interfering check.

to next instruction is enough to get better result. For some special case, this patch could get significant performance boost. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/llvm/llvm_gen_backend.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backend/sr

Re: [Beignet] [PATCH 2/2] Fix DRM Memory leak BUG

t event) blocking event wait here is really not good idea. Thanks, Zhigang Gong. > > The rare usage of event from the PSieve-CUDA case: > checkCUDAErr(clEnqueueReadBuffer(commandQueue, > d_factor_found, > CL_TRUE, > 0, > cthread_coun

Re: [Beignet] [PATCH v2 1/2] GBE: continue to refine interfering check.

to check interference between local values. This is a good point, I will add comments or assertion to restrict the use scenarios of these helper routines. Thanks, Zhigang Gong. On Wed, Sep 23, 2015 at 09:58:29AM +0800, Zhigang Gong wrote: > On Wed, Sep 23, 2015 at 03:05:18AM +, Song, Ruiling wr

[Beignet] [PATCH 4/8] GBE: add some dag helper routines to check registers' interfering.

These helper function will be used in further phi mov optimization. v2: remove the useless debug message code. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 100 +++ backend/src/ir/value.hpp | 13 ++ 2

[Beignet] [PATCH 2/8] GBE: refine liveness analysis.

Only in gen backend stage, we need to take care of the special extra liveout and uniform analysis. In IR stage, we don't need to handle them. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.cpp | 2 +- backend/src/ir/liveness.cpp

[Beignet] [PATCH 6/8] GBE: continue to refine interfering check.

of interleve check functions of DAG class. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 133 --- backend/src/ir/value.hpp | 13 +++-- 2 files changed, 123 insertions(+), 23 deletions(-) diff --git a/backend/

[Beignet] [PATCH 7/8] GBE: Fix one DAG analysis issue and enable multiple round phi copy elimination.

-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 8 backend/src/llvm/llvm_gen_backend.cpp | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/backend/src/ir/value.cpp b/backend/src/ir/value.cpp index d2f0c2e..d5215cb

Re: [Beignet] [PATCH 0/5] curbe register allocation refactor and optimization

Ping for review. Thanks. On Mon, Sep 14, 2015 at 02:19:31PM +0800, Zhigang Gong wrote: > This patch series is to fix the hacky curbe register allocation. > Before, we treat these registers totally different way to the other > normal registers. Then we do a lot of patch work in the back

Re: [Beignet] [PATCH 2/2] Fix DRM Memory leak BUG

in the wait list of the last event has user call back function registered and has been missed. We may need to check all the wait list of the last event before we do a locking event updating here. Thanks, Zhigang Gong. On Mon, Sep 21, 2015 at 04:41:52PM +0800, Pan Xiuli wrote: > This bug is cased by ev

Re: [Beignet] [PATCH 3/5] GBE: add two helper routines for liveness partially update.

eed to re-write the uniform analysis completely in the future. But for now, I prefer to keep it as is. Thanks, Zhigang Gong. > > Thanks! > Ruiling > > > + bb->definedPhiRegs.insert(to); > > +

Re: [Beignet] [PATCH 5/5] GBE: implement further phi mov optimization based on intra-BB interefering analysis.

; + const_cast(phiSrcUseInsn)->remove(); > > + continue; > > +} > > +replaceSrc(const_cast(phiSrcUseInsn), > > phiCopySrc, > > phiCopy); > > + } > > + > > + replaced

Re: [Beignet] [PATCH] GBE: avoid vector registers when there is high register pressure.

add more pressure to the register allocation" Right, the comments are out-of-date now and need to be removed. Thanks, Zhigang Gong. > > Thanks! > Ruiling > 2015-09-17 8:39 GMT+08:00 Zhigang Gong <zhigang.g...@linux.intel.com>: > > > Ping for review. > > Thanks. &g

Re: [Beignet] [PATCH 1/2] GBE: continue to refine interfering check.

Ping for review. Thanks. On Sun, Sep 06, 2015 at 03:05:00PM +0800, Zhigang Gong wrote: > More aggresive interfering check, even if both registers are in > Livein set or Liveout set, they are still possible not interfering > to each other. > > Signed-off-by: Zhigang Gong <zhig

Re: [Beignet] [PATCH 1/5] GBE: refine Phi copy interfering check.

Ping for review. Thanks. On Tue, Sep 01, 2015 at 12:04:59PM +0800, Zhigang Gong wrote: > If the PHI source register's definition instruction uses the > phi register, it is not a interfere. For an example: > > MOV %phi, %phicopy > ... > ADD %phiSrcDef, %phi, tmp > ... >

[Beignet] [PATCH] GBE: implement pre-register-allocation instruction scheduling.

ling which will try to get as much ILP as possible. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_insn_scheduling.cpp | 137 +++- 1 file changed, 116 insertions(+), 21 deletions(-) diff --git a/backend/src/backend/gen_insn_schedulin

Re: [Beignet] [PATCH] remove register name which is no longer there

This patch LGTM, and my patchset includes this change. I will rebase after both of them got reviewed. Thanks. On Mon, Sep 14, 2015 at 06:56:37AM +0800, Guo Yejun wrote: > 8b9672ae40 removed the register laneid and should remove the name > at same patch, but missed. > > Signed-off-by: Guo Yejun

Re: [Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

Please ignore this patch, it seems there are some issues after this change. I will look into it and send it again when things got fixed. Thanks, Zhigang Gong. On Mon, Sep 14, 2015 at 02:19:36PM +0800, Zhigang Gong wrote: > Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> > --- &g

[Beignet] [PATCH 2/5] GBE: refine longjmp checking.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_insn_selection.cpp | 2 +- backend/src/ir/function.hpp| 17 + 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backe

[Beignet] [PATCH 4/5] GBE: don't always allocate ir::ocl::one/zero

Use liveness information, we can only allocate them on demand. And they could be treated as non-curbe-payload register. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen_context.cpp| 10 -- backend/src/backend/gen_reg_allocation.cp

[Beignet] [PATCH 3/5] GBE: don't treat btiUtil as a curbe payload register.

this issue completely. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/gen8_context.cpp | 10 +- backend/src/backend/gen_context.cpp| 47 + backend/src/backend/gen_context.hpp| 4 +- backend/src/backend/gen_insn_selection.cpp

[Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.hpp| 2 +- backend/src/backend/gen_reg_allocation.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/backend/src/backend/context.hpp b/backend/src/backend/context.hpp

[Beignet] [PATCH 1/5] GBE: refactor curbe register allocation.

is to eliminate the ugly curbe patch list handling in backend. After this patch, the curbe register handling is much cleaner than before. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/context.cpp| 14 backend/src/backend/context.hpp

[Beignet] [PATCH 0/5] curbe register allocation refactor and optimization

liveness information. At most cases, it can save one or two registers. This patch also fixed one longjmp issue. The previous method is too inaccurate which is according basib block numbers. This patch is a preparation of next patch set which is to further optimize register allocation. Zhigang Gong

Re: [Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

It turns out that the issue was not caused by this patch, so this patch is good to go. I already submitted another patch to fix that liveness bug. Thanks, Zhigang Gong. > -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of > Zhigang Go

[Beignet] [PATCH] GBE: fix a zero/one's liveness bug.

This is a long standing bug, and is exposed by my latest register allocation refinement patchset. ir::ocl::zero and ir::ocl::one are global registers, we have to compute its liveness information carefully, not just get a local interval ID. Signed-off-by: Zhigang Gong <zhigang.g...@intel.

[Beignet] [PATCH] GBE: fix build error with LLVM 3.5 and previous version.

Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/backend/program.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/program.cpp b/backend/src/backend/program.cpp index 330bead..57a5037 100644 --- a/backend/src/backend/progr

Re: [Beignet] [PATCH 3/3] add optimization for local copy propagation

eignet-boun...@lists.freedesktop.org] On Behalf Of > Guo, Yejun > Sent: Monday, September 7, 2015 2:11 PM > To: Zhigang Gong; beignet@lists.freedesktop.org > Subject: Re: [Beignet] [PATCH 3/3] add optimization for local copy propagation > > It is expected that there will be improveme

Re: [Beignet] [PATCH 3/3] add optimization for local copy propagation

> -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of > Guo, Yejun > Sent: Monday, September 7, 2015 8:27 PM > To: Zhigang Gong; beignet@lists.freedesktop.org > Subject: Re: [Beignet] [PATCH 3/3] add optimization for loca

Re: [Beignet] [PATCH 3/3] add optimization for local copy propagation

Is there any evidence that this optimization could bring actual improvement? I doubt it because it doesn't reduce any instruction. Actually, if the %42 is not in the liveout set of current BB, then the MOV could be removed, the exactly same optimization logic has been implemented in the GEN IR

[Beignet] [PATCH v2 1/2] GBE: continue to refine interfering check.

%r1 and %r2 are in the BBn's liveout set, but %r2 is not defined or used in BBn. The previous implementation ignore this BB which is incorrect. As %r1 was modified to a different value, it means %r1 could not be replaced with %r2 in this case. Signed-off-by: Zhigang Gong <zhigang.g...@intel.

[Beignet] [PATCH 1/2] GBE: continue to refine interfering check.

More aggresive interfering check, even if both registers are in Livein set or Liveout set, they are still possible not interfering to each other. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 117 ++- backe

[Beignet] [PATCH 2/2] GBE: Fix one DAG analysis issue and enable multiple round phi copy elimination.

the definition of %foo in BB0 to BB1, the previous implementation will ignore it because %foo is killed in BB1, this is a bug. This patch fixes it. And thus we can enable multiple round phi copy elimination safely. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/val

[Beignet] [PATCH v2 4/5] GBE: add some dag helper routines to check registers' interfering.

These helper function will be used in further phi mov optimization. v2: remove the useless debug message code. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 100 +++ backend/src/ir/value.hpp | 13 ++ 2

[Beignet] [PATCH] GBE: Use addRemappedFile to avoid creating temporary cl source file.

in the current directory, beignet will not find it. 2. Even if the probram add a "-I." option manually, beignet will search /tmp firstly, and if there is a .h file in /tmp/ with the eaxct same file name, beignet will the file located in /tmp. Signed-off-by: Zhigang Gong <zhigang.g

[Beignet] [PATCH 4/5] GBE: add some dag helper routines to check registers' interfering.

These helper function will be used in further phi mov optimization. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/ir/value.cpp | 102 +++ backend/src/ir/value.hpp | 13 ++ 2 files changed, 115 insertions(+) diff

[Beignet] [PATCH 1/5] GBE: refine Phi copy interfering check.

to next instruction is enough to get better result. For some special case, this patch could get significant performance boost. Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> --- backend/src/llvm/llvm_gen_backend.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backend/sr

Re: [Beignet] [PATCH 4/4] GBE: a potential bug in instruction scheduling.

] [PATCH 4/4] GBE: a potential bug in instruction scheduling. Luo Xionghu Best Regards -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Zhigang Gong Sent: Thursday, August 13, 2015 10:24 AM To: beignet@lists.freedesktop.org Cc: Gong

Re: [Beignet] [PATCH V2] fix issue when build against llvm3.3

Pushed, thanks. On Thu, Aug 13, 2015 at 08:20:44AM +, Song, Ruiling wrote: LGTM -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Guo Yejun Sent: Thursday, August 13, 2015 3:35 AM To: beignet@lists.freedesktop.org Cc: Guo,

[Beignet] [PATCH 1/4] GBE: fix the broken image_1d_buffer write.

We should treat it as a 2D image as image 1d buffer may be exceed the 1D image size restrication. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- backend/src/libocl/src/ocl_image.cl | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/backend/src/libocl/src

[Beignet] [PATCH 2/4] utests: refine image 1d buffer test case.

We need to test large image 1d buffer read and write testing. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- kernels/image_1D_buffer.cl | 11 ++- utests/image_1D_buffer.cpp | 73 ++ 2 files changed, 32 insertions(+), 52 deletions(-) diff

[Beignet] [PATCH 4/4] GBE: a potential bug in instruction scheduling.

ENDIF should be treated as barrier-like instruction in instruction scheduling. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- backend/src/backend/gen_insn_scheduling.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_insn_scheduling.cpp b

Re: [Beignet] [PATCH] libocl: fix degrees function precision issue.

LGTM, thx. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of xionghu@intel.com Sent: Thursday, August 6, 2015 3:58 PM To: beignet@lists.freedesktop.org Cc: xionghu@intel.com Subject: [Beignet] [PATCH] libocl: fix degrees function

Re: [Beignet] [PATCH v2] GetEventProfilingInfo could query all event status.

to clGetEventProfilingInfo(). The patch is as below, From a5a1b3f372d17f26cc20fba078490b61614f07e5 Mon Sep 17 00:00:00 2001 From: Zhigang Gong zhigang.g...@intel.com Date: Tue, 4 Aug 2015 13:21:27 +0800 Subject: [PATCH] runtime: always try to update event status in clGetEventProfilingInfo(). Some applications forgot

Re: [Beignet] [PATCH v2] GetEventProfilingInfo could query all event status.

() then it will cause functional error, I will agree that we need both patches. Even though xionghu's patch need to refine the commit log message, as it is not to fix GetEventProfilingInfo() issue. Thanks, Zhigang Gong. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org

Re: [Beignet] [PATCH v2] GetEventProfilingInfo could query all event status.

to solve this problem. Thanks, Zhigang Gong. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Yang, Rong R Sent: Wednesday, August 5, 2015 11:38 AM To: Zhigang Gong; Luo, Xionghu Cc: beignet@lists.freedesktop.org Subject: Re: [Beignet

Re: [Beignet] [PATCH v2] GetEventProfilingInfo could query all event status.

-Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Yang, Rong R Sent: Wednesday, August 5, 2015 1:05 PM To: Zhigang Gong; Luo, Xionghu Cc: beignet@lists.freedesktop.org Subject: Re: [Beignet] [PATCH v2] GetEventProfilingInfo could query

Re: [Beignet] thread safety and OpenMP

at bugzilla and describe how to reproduce the issue. The bugzilla link is as below: https://bugs.freedesktop.org/enter_bug.cgi?product=Beignet Thanks, Zhigang Gong. -Original Message- From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Gerald Baier Sent: Thursday, July 2

Re: [Beignet] thread safety and OpenMP

Thanks for the testing, but my latest patch is still under review, could you apply it manually and try again? The patch is at http://lists.freedesktop.org/archives/beignet/2015-July/005871.html. Thanks, Zhigang Gong. -Original Message- From: Beignet [mailto:beignet-boun

Re: [Beignet] [PATCH 2/2] Remove deprecated function cl_context_get_static_kernel().

...@lists.freedesktop.org] On Behalf Of Zhigang Gong Sent: Thursday, July 16, 2015 12:48 PM To: beignet@lists.freedesktop.org Cc: Zhigang Gong Subject: [Beignet] [PATCH 2/2] Remove deprecated function cl_context_get_static_kernel(). Also fix a spelling bug - s/internel/internal. Signed

[Beignet] [PATCH 1/2] runtime: fix a builtin-kernel related thread safe bug.

This patch fixed two thread-safe bugs in the builtin-kernel usage code path. 1. The builtin kernel array itself need to be protected. 2. Each caller need to get a dup of the builtin kernel, rather than share the same kernel structure. Signed-off-by: Zhigang Gong zhigang.g...@intel.com

[Beignet] [PATCH 2/2] Remove deprecated function cl_context_get_static_kernel().

Also fix a spelling bug - s/internel/internal. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- src/cl_context.c | 73 +--- src/cl_context.h | 2 +- 2 files changed, 12 insertions(+), 63 deletions(-) diff --git a/src/cl_context.c b/src

Re: [Beignet] [PATCH 1/2] Fixed a thread safe bug.

Please ignore this version as I forgot to remove the debug message. Just sent out the version 2. Thanks, Zhigang Gong. On Wed, Jul 15, 2015 at 08:54:33AM +0800, Zhigang Gong wrote: From: Zhigang Gong zhigang.g...@linux.intel.com last_event and current_event should be thread private data

[Beignet] [Patch v2 1/2] Fixed a thread safe bug.

From: Zhigang Gong zhigang.g...@linux.intel.com last_event and current_event should be thread private data. Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com --- src/cl_api.c | 2 +- src/cl_command_queue.c | 17 +++-- src/cl_command_queue.h | 2 -- src/cl_event.c

[Beignet] [PATCH] runtime: Need to separate atomic in L3 test and SLM test in self_test().

for both atomic in L3 and SLM not working case. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- src/cl_device_id.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/cl_device_id.c b/src/cl_device_id.c index f995550..b788137 100644 --- a/src

Re: [Beignet] [PATCH 1/2] fix global variable out of boundary writing in libocl.

Nice catch, LGTM, thanks. On Fri, Jun 12, 2015 at 09:10:00AM +0800, xionghu@intel.com wrote: From: Luo Xionghu xionghu@intel.com need minus one when fill '\0' to sizeof char type array. Signed-off-by: Luo Xionghu xionghu@intel.com --- src/cl_extensions.c | 2 +- 1 file

Re: [Beignet] [PATCH v2] reimplement structurize algorithm.

LGTM, thanks. On Mon, Jun 08, 2015 at 03:19:47PM +0800, xionghu@intel.com wrote: From: Luo Xionghu xionghu@intel.com serial, loop and if pattern match from top to down. v2: remove recursive sort since the blocks are in order already, just copy it from Function; add comments to

Re: [Beignet] [PATCH V2] GBE: Support storing/loading pointers to/from private array

LGTM, pushed. Thanks, Zhigang Gong. On Tue, Jun 02, 2015 at 03:26:28PM +0800, Ruiling Song wrote: The idea is create two additional array for holding pointer-base and bti. v2: When pointer operand is exactly the pointer origin, we do not insert into pointerOrigMap. so, don't directly find

Re: [Beignet] [PATCH] GBE: fix one potential register spilling bug.

Thanks for the careful review comment. Just fixed it and pushed. On Tue, Jun 02, 2015 at 06:29:41AM +, Song, Ruiling wrote: if ((regSize == ctx.getSimdWidth()/8 * GEN_REG_SIZE family == ir::FAMILY_DWORD) - || (regSize == 2 * ctx.getSimdWidth()/8 * GEN_REG_SIZE

Re: [Beignet] [PATCH 1/2] GBE: Fix a typo that cause gpu hang.

The patchset LGTM, will push latter. Thanks, Zhigang Gong. On Mon, Jun 01, 2015 at 09:43:06AM +0800, Ruiling Song wrote: Signed-off-by: Ruiling Song ruiling.s...@intel.com --- backend/src/backend/gen75_encoder.cpp | 2 +- backend/src/backend/gen8_encoder.cpp | 2 +- 2 files changed, 2

Re: [Beignet] [PATCH] GBE: Support storing/loading pointers to/from private array

It seems that this patch cause one regression in the unit test cases. You can reproduce it as below: utests/utest_run compiler_local_slm Thanks, Zhigang Gong. On Thu, May 21, 2015 at 04:39:05PM +0800, Ruiling Song wrote: The idea is create two additional array for holding pointer-base and bti

Re: [Beignet] [PATCH] Fix a indirect argument load bug.

LGTM, pushed, thanks. On Thu, May 21, 2015 at 11:31:21AM +0800, Yang Rong wrote: If use arg as non add instruction's source directly, for example phi and selection, there is no add, just skip it. Signed-off-by: Yang Rong rong.r.y...@intel.com --- backend/src/ir/lowering.cpp | 1 + 1

[Beignet] [PATCH] GBE: fix one potential register spilling bug.

unecessary complexity, this patch is to gather the partially writting registers and don't put these register to spill candidate set. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- backend/src/backend/gen_insn_selection.cpp | 45 +++--- backend/src/backend

Re: [Beignet] Loop unrolling?

Beignet supports loop unrolling. We use the LLVM LoopUnrollPass to do the unrolling. And the Clang's unrolling pragma is supported in beignet. On Thu, May 21, 2015 at 01:14:13PM +0200, Stojan Dimitrovski wrote: Hi, Does the Beignet compiler support loop unrolling, if so what are the

[Beignet] [PATCH v2] build: use EXECUTE_PROCESS to replace the deprecated EXEC_PROGRAM.

. v2: fix the error in examples/CMakeLists.txt. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- examples/CMakeLists.txt | 12 ++-- utests/CMakeLists.txt | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index

[Beignet] [PATCH] build: use EXECUTE_PROCESS to replace the deprecated EXEC_PROGRAM.

. Signed-off-by: Zhigang Gong zhigang.g...@intel.com --- examples/CMakeLists.txt | 8 utests/CMakeLists.txt | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt index 904f259..3dc5e24 100644 --- a/examples

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