From: Junyan He <junyan...@linux.intel.com> Signed-off-by: Junyan He <junyan...@linux.intel.com> Reviewed-by: Yang Rong <rong.r.y...@intel.com> --- backend/src/backend/gen_context.cpp | 3 ++ backend/src/backend/gen_context.hpp | 1 + .../src/backend/gen_insn_gen7_schedule_info.hxx | 1 + backend/src/backend/gen_insn_selection.cpp | 34 ++++++++++++++++++++++ backend/src/backend/gen_insn_selection.hpp | 1 + backend/src/backend/gen_insn_selection.hxx | 1 + 6 files changed, 41 insertions(+)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 05359af..ed6c9f0 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -2345,6 +2345,9 @@ namespace gbe p->TYPED_WRITE(header, true, bti); } + void GenContext::emitWorkGroupOpInstruction(const SelectionInstruction &insn) { + } + void GenContext::setA0Content(uint16_t new_a0[16], uint16_t max_offset, int sz) { if (sz == 0) sz = 8; diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp index f050548..d1294fc 100644 --- a/backend/src/backend/gen_context.hpp +++ b/backend/src/backend/gen_context.hpp @@ -181,6 +181,7 @@ namespace gbe virtual void emitI64MULInstruction(const SelectionInstruction &insn); virtual void emitI64DIVREMInstruction(const SelectionInstruction &insn); virtual void emitF64DIVInstruction(const SelectionInstruction &insn); + void emitWorkGroupOpInstruction(const SelectionInstruction &insn); void scratchWrite(const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode); void scratchRead(const GenRegister dst, const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode); unsigned beforeMessage(const SelectionInstruction &insn, GenRegister bti, GenRegister flagTemp, GenRegister btiTmp, unsigned desc); diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx index 792014f..49e328f 100644 --- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx +++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx @@ -51,3 +51,4 @@ DECL_GEN7_SCHEDULE(I64MUL, 20, 40, 20) DECL_GEN7_SCHEDULE(I64SATADD, 20, 40, 20) DECL_GEN7_SCHEDULE(I64SATSUB, 20, 40, 20) DECL_GEN7_SCHEDULE(F64DIV, 20, 40, 20) +DECL_GEN7_SCHEDULE(WorkGroupOp, 80, 1, 1) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 6511f56..89adca4 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -697,6 +697,9 @@ namespace gbe void I64REM(Reg dst, Reg src0, Reg src1, GenRegister *tmp, int tmp_int); /*! double division */ void F64DIV(Reg dst, Reg src0, Reg src1, GenRegister* tmp, int tmpNum); + /*! Work Group Operations */ + void WORKGROUP_OP(uint32_t wg_op, Reg dst, GenRegister src, GenRegister nextThreadID, + GenRegister threadID, GenRegister threadn, GenRegister tmp); /* common functions for both binary instruction and sel_cmp and compare instruction. It will handle the IMM or normal register assignment, and will try to avoid LOADI as much as possible. */ @@ -2036,6 +2039,20 @@ namespace gbe insn->dst(i + 1) = tmp[i]; } + void Selection::Opaque::WORKGROUP_OP(uint32_t wg_op, Reg dst, GenRegister src, GenRegister nextThreadID, + GenRegister threadID, GenRegister threadn, GenRegister tmp) { + SelectionInstruction *insn = this->appendInsn(SEL_OP_WORKGROUP_OP, 3, 4); + insn->extra.workgroupOp = wg_op; + insn->dst(0) = dst; + insn->dst(1) = nextThreadID; + insn->dst(2) = tmp; + + insn->src(0) = src; + insn->src(1) = nextThreadID; + insn->src(2) = threadID; + insn->src(3) = threadn; + } + // Boiler plate to initialize the selection library at c++ pre-main static SelectionLibrary *selLib = NULL; static void destroySelectionLibrary(void) { GBE_DELETE(selLib); } @@ -6553,9 +6570,26 @@ namespace gbe /* Third, get the next thread ID which we will Forward MSG to. */ GenRegister nextThreadID = getNextThreadID(sel, slmAddr); + GenRegister threadID = sel.selReg(ocl::threadid, ir::TYPE_U32); + GenRegister threadNum = sel.selReg(ocl::threadn, ir::TYPE_U32); + GenRegister tmp = GenRegister::retype(sel.selReg(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD); + + const Type type = insn.getType(); + const GenRegister dst = sel.selReg(insn.getDst(0), type); + const uint32_t srcNum = insn.getSrcNum(); + GBE_ASSERT(srcNum == 3); + GBE_ASSERT(insn.getSrc(0) == ir::ocl::threadn); + GBE_ASSERT(insn.getSrc(1) == ir::ocl::threadid); + GenRegister src = sel.selReg(insn.getSrc(2), type); + sel.push(); { + sel.curr.flag = 0; + sel.curr.subFlag = 1; + sel.WORKGROUP_OP(workGroupOp, dst, src, nextThreadID, threadID, threadNum, tmp); + } sel.pop(); } else { GBE_ASSERT(0); } + return true; } DECL_CTOR(WorkGroupInstruction, 1, 1); diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp index f51c905..9e4aee9 100644 --- a/backend/src/backend/gen_insn_selection.hpp +++ b/backend/src/backend/gen_insn_selection.hpp @@ -132,6 +132,7 @@ namespace gbe uint32_t barrierType; bool longjmp; uint32_t indirect_offset; + uint32_t workgroupOp; } extra; /*! Gen opcode */ uint8_t opcode; diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx index f6ed284..7c4991a 100644 --- a/backend/src/backend/gen_insn_selection.hxx +++ b/backend/src/backend/gen_insn_selection.hxx @@ -98,3 +98,4 @@ DECL_SELECTION_IR(ELSE, UnaryInstruction) DECL_SELECTION_IR(READ_ARF, UnaryInstruction) DECL_SELECTION_IR(WHILE, UnaryInstruction) DECL_SELECTION_IR(F64DIV, F64DIVInstruction) +DECL_SELECTION_IR(WORKGROUP_OP, WorkGroupOpInstruction) -- 2.5.0 _______________________________________________ Beignet mailing list Beignet@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet