Use wait function to extend a debug function: void debugwait(void) This function can hang the gpu unless gpu reset or host send something to let it go. EXTREMELY DANGEROUS for machines turn off hangcheck
v2: Fix some bugs, and add setting predicate and execwidth, also modify some inst scheduling v3: Add push and pop in insturction selection, and set nomask with execwidth. Signed-off-by: Pan Xiuli <xiuli....@intel.com> --- backend/src/backend/gen_context.cpp | 2 +- backend/src/backend/gen_encoder.cpp | 1 + backend/src/backend/gen_insn_scheduling.cpp | 1 + backend/src/backend/gen_insn_selection.cpp | 28 +++++++++++++++++++++++++-- backend/src/backend/gen_insn_selection.hpp | 1 + backend/src/ir/instruction.cpp | 30 +++++++++++++++++++++++++++++ backend/src/ir/instruction.hpp | 9 +++++++++ backend/src/ir/instruction.hxx | 1 + backend/src/libocl/include/ocl_sync.h | 1 + backend/src/libocl/src/ocl_barrier.ll | 6 ++++++ backend/src/libocl/src/ocl_sync.cl | 1 + backend/src/llvm/llvm_gen_backend.cpp | 6 ++++++ backend/src/llvm/llvm_gen_ocl_function.hxx | 2 ++ 13 files changed, 86 insertions(+), 3 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 9868043..d843620 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -1802,7 +1802,7 @@ namespace gbe } void GenContext::emitWaitInstruction(const SelectionInstruction &insn) { - p->WAIT(); + p->WAIT(insn.extra.waitType); } void GenContext::emitBarrierInstruction(const SelectionInstruction &insn) { diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp index 1ad4f01..7c4357a 100644 --- a/backend/src/backend/gen_encoder.cpp +++ b/backend/src/backend/gen_encoder.cpp @@ -996,6 +996,7 @@ namespace gbe void GenEncoder::WAIT(uint32_t n) { GenNativeInstruction *insn = this->next(GEN_OPCODE_WAIT); + GBE_ASSERT(curr.predicate == GEN_PREDICATE_NONE); GenRegister src = GenRegister::notification0(n); this->setDst(insn, GenRegister::null()); this->setSrc0(insn, src); diff --git a/backend/src/backend/gen_insn_scheduling.cpp b/backend/src/backend/gen_insn_scheduling.cpp index 358a2ce..8ee5e48 100644 --- a/backend/src/backend/gen_insn_scheduling.cpp +++ b/backend/src/backend/gen_insn_scheduling.cpp @@ -589,6 +589,7 @@ namespace gbe || node->insn.opcode == SEL_OP_ENDIF || node->insn.opcode == SEL_OP_WHILE || node->insn.opcode == SEL_OP_READ_ARF + || node->insn.opcode == SEL_OP_WAIT || node->insn.opcode == SEL_OP_BARRIER) tracker.makeBarrier(insnID, insnNum); } diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 508a5ea..0122377 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -619,7 +619,7 @@ namespace gbe /*! No-op */ void NOP(void); /*! Wait instruction (used for the barrier) */ - void WAIT(void); + void WAIT(uint32_t n = 0); /*! Atomic instruction */ void ATOMIC(Reg dst, uint32_t function, uint32_t srcNum, Reg src0, Reg src1, Reg src2, GenRegister bti, vector<GenRegister> temps); /*! Read 64 bits float/int array */ @@ -1289,7 +1289,11 @@ namespace gbe void Selection::Opaque::EOT(void) { this->appendInsn(SEL_OP_EOT, 0, 0); } void Selection::Opaque::NOP(void) { this->appendInsn(SEL_OP_NOP, 0, 0); } - void Selection::Opaque::WAIT(void) { this->appendInsn(SEL_OP_WAIT, 0, 0); } + void Selection::Opaque::WAIT(uint32_t n) + { + SelectionInstruction *insn = this->appendInsn(SEL_OP_WAIT, 0, 0); + insn->extra.waitType = n; + } void Selection::Opaque::READ64(Reg addr, const GenRegister *dst, @@ -3412,6 +3416,25 @@ namespace gbe DECL_CTOR(SyncInstruction, 1,1); }; + /*! Wait instruction */ + DECL_PATTERN(WaitInstruction) + { + INLINE bool emitOne(Selection::Opaque &sel, const ir::WaitInstruction &insn, bool &markChildren) const + { + using namespace ir; + // Debugwait will use reg 1, which is different from barrier + sel.push(); + sel.curr.noMask = 1; + sel.curr.execWidth = 1; + sel.curr.predicate = GEN_PREDICATE_NONE; + sel.WAIT(1); + sel.pop(); + return true; + } + + DECL_CTOR(WaitInstruction, 1,1); + }; + INLINE uint32_t getByteScatterGatherSize(Selection::Opaque &sel, ir::Type type) { using namespace ir; switch (type) { @@ -5838,6 +5861,7 @@ namespace gbe this->insert<SimdShuffleInstructionPattern>(); this->insert<IndirectMovInstructionPattern>(); this->insert<NullaryInstructionPattern>(); + this->insert<WaitInstructionPattern>(); // Sort all the patterns with the number of instructions they output for (uint32_t op = 0; op < ir::OP_INVALID; ++op) diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp index 578db41..2aba7bd 100644 --- a/backend/src/backend/gen_insn_selection.hpp +++ b/backend/src/backend/gen_insn_selection.hpp @@ -136,6 +136,7 @@ namespace gbe uint16_t lut_sub:2; }; uint32_t barrierType; + uint32_t waitType; bool longjmp; uint32_t indirect_offset; } extra; diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index 84ad5c6..a2b8a14 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir/instruction.cpp @@ -897,6 +897,21 @@ namespace ir { Register dst[0], src[0]; }; + /*! Wait instructions */ + class ALIGNED_INSTRUCTION WaitInstruction : + public BasePolicy, + public NSrcPolicy<WaitInstruction, 0>, + public NDstPolicy<WaitInstruction, 0> + { + public: + INLINE WaitInstruction() { + this->opcode = OP_WAIT; + } + INLINE bool wellFormed(const Function &fn, std::string &why) const; + INLINE void out(std::ostream &out, const Function &fn) const; + Register dst[0], src[0]; + }; + #undef ALIGNED_INSTRUCTION ///////////////////////////////////////////////////////////////////////// @@ -1195,6 +1210,8 @@ namespace ir { { return true; } INLINE bool GetImageInfoInstruction::wellFormed(const Function &fn, std::string &why) const { return true; } + INLINE bool WaitInstruction::wellFormed(const Function &fn, std::string &why) const + { return true; } // Ensure that types and register family match @@ -1459,6 +1476,9 @@ namespace ir { out << "." << syncStr[field]; } + INLINE void WaitInstruction::out(std::ostream &out, const Function &fn) const { + this->outOpcode(out); + } } /* namespace internal */ @@ -1600,6 +1620,10 @@ START_INTROSPECTION(LabelInstruction) #include "ir/instruction.hxx" END_INTROSPECTION(LabelInstruction) +START_INTROSPECTION(WaitInstruction) +#include "ir/instruction.hxx" +END_INTROSPECTION(WaitInstruction) + START_INTROSPECTION(VmeInstruction) #include "ir/instruction.hxx" END_INTROSPECTION(VmeInstruction) @@ -1747,6 +1771,7 @@ END_FUNCTION(Instruction, Register) return opcode == OP_STORE || opcode == OP_TYPED_WRITE || opcode == OP_SYNC || + opcode == OP_WAIT || opcode == OP_ATOMIC; } @@ -2080,6 +2105,11 @@ DECL_MEM_FN(MemInstruction, void, setBtiReg(Register reg), setBtiReg(reg)) return internal::GetImageInfoInstruction(infoType, dst, imageIndex, infoReg).convert(); } + // WAIT + Instruction WAIT(void) { + return internal::WaitInstruction().convert(); + } + std::ostream &operator<< (std::ostream &out, const Instruction &insn) { const Function &fn = insn.getFunction(); const BasicBlock *bb = insn.getParent(); diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp index 6ed8893..24fd981 100644 --- a/backend/src/ir/instruction.hpp +++ b/backend/src/ir/instruction.hpp @@ -554,6 +554,13 @@ namespace ir { static bool isClassOf(const Instruction &insn); }; + /*! Indirect Move instruction */ + class WaitInstruction : public Instruction { + public: + /*! Return true if the given instruction is an instance of this class */ + static bool isClassOf(const Instruction &insn); + }; + /*! Specialize the instruction. Also performs typechecking first based on the * opcode. Crashes if it fails */ @@ -771,6 +778,8 @@ namespace ir { Instruction GET_IMAGE_INFO(int infoType, Register dst, uint8_t imageIndex, Register infoReg); /*! label labelIndex */ Instruction LABEL(LabelIndex labelIndex); + /*! wait */ + Instruction WAIT(void); } /* namespace ir */ } /* namespace gbe */ diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx index 27d59a9..fdde98a 100644 --- a/backend/src/ir/instruction.hxx +++ b/backend/src/ir/instruction.hxx @@ -107,3 +107,4 @@ DECL_INSN(IF, BranchInstruction) DECL_INSN(ENDIF, BranchInstruction) DECL_INSN(ELSE, BranchInstruction) DECL_INSN(WHILE, BranchInstruction) +DECL_INSN(WAIT, WaitInstruction) diff --git a/backend/src/libocl/include/ocl_sync.h b/backend/src/libocl/include/ocl_sync.h index 18090d5..1d90cae 100644 --- a/backend/src/libocl/include/ocl_sync.h +++ b/backend/src/libocl/include/ocl_sync.h @@ -31,5 +31,6 @@ OVERLOADABLE void barrier(cl_mem_fence_flags flags); void mem_fence(cl_mem_fence_flags flags); void read_mem_fence(cl_mem_fence_flags flags); void write_mem_fence(cl_mem_fence_flags flags); +OVERLOADABLE void debugwait(void); #endif /* __OCL_SYNC_H__ */ diff --git a/backend/src/libocl/src/ocl_barrier.ll b/backend/src/libocl/src/ocl_barrier.ll index 2765a71..9416f80 100644 --- a/backend/src/libocl/src/ocl_barrier.ll +++ b/backend/src/libocl/src/ocl_barrier.ll @@ -12,6 +12,7 @@ declare i32 @_get_global_mem_fence() nounwind alwaysinline declare void @__gen_ocl_barrier_local() nounwind alwaysinline noduplicate declare void @__gen_ocl_barrier_global() nounwind alwaysinline noduplicate declare void @__gen_ocl_barrier_local_and_global() nounwind alwaysinline noduplicate +declare void @__gen_ocl_debugwait() nounwind alwaysinline noduplicate define void @_Z7barrierj(i32 %flags) nounwind noduplicate alwaysinline { %1 = icmp eq i32 %flags, 3 @@ -40,3 +41,8 @@ barrier_global: done: ret void } + +define void @_Z9debugwaitv() nounwind noduplicate alwaysinline { + call void @__gen_ocl_debugwait() + ret void +} diff --git a/backend/src/libocl/src/ocl_sync.cl b/backend/src/libocl/src/ocl_sync.cl index d008639..70d6f26 100644 --- a/backend/src/libocl/src/ocl_sync.cl +++ b/backend/src/libocl/src/ocl_sync.cl @@ -20,6 +20,7 @@ void __gen_ocl_barrier_local(void); void __gen_ocl_barrier_global(void); void __gen_ocl_barrier_local_and_global(void); +void __gen_ocl_debugwait(void); void mem_fence(cl_mem_fence_flags flags) { } diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index fdc8844..b321c7c 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -3581,6 +3581,7 @@ namespace gbe this->newRegister(&I); break; case GEN_OCL_PRINTF: + case GEN_OCL_DEBUGWAIT: break; case GEN_OCL_NOT_FOUND: default: @@ -4340,6 +4341,11 @@ namespace gbe ctx.SIMD_SHUFFLE(getType(ctx, I.getType()), dst, src0, src1); break; } + case GEN_OCL_DEBUGWAIT: + { + ctx.WAIT(); + break; + } default: break; } } diff --git a/backend/src/llvm/llvm_gen_ocl_function.hxx b/backend/src/llvm/llvm_gen_ocl_function.hxx index 3fbf847..ba71c68 100644 --- a/backend/src/llvm/llvm_gen_ocl_function.hxx +++ b/backend/src/llvm/llvm_gen_ocl_function.hxx @@ -172,3 +172,5 @@ DECL_LLVM_GEN_FUNCTION(VME, __gen_ocl_vme) // printf function DECL_LLVM_GEN_FUNCTION(PRINTF, __gen_ocl_printf) +// debug wait function +DECL_LLVM_GEN_FUNCTION(DEBUGWAIT, __gen_ocl_debugwait) -- 2.1.4 _______________________________________________ Beignet mailing list Beignet@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet