Good morning Luke,
> > Another point to ponder is test modes.
> > In mass production you need test modes.
>
> > (Sure, an attacker can try targeted ESD at the `TESTMODE` flip-flop
> > repeatedly, but this risks also flipping other scan flip-flops that contain
> > the data that is being
(cc'ing over to libre-soc-dev)
https://lists.linuxfoundation.org/pipermail/bitcoin-dev/2021-February/018392.html
On Thu, Feb 11, 2021 at 8:21 AM ZmnSCPxj wrote:
> > i was stunned to learn that in a 28nm ASIC, 50% of it is repeater-buffers!
>
> Well, that surprises me as well.
> [...]
> So I
On Sat, Feb 13, 2021 at 3:01 PM Bryan Bishop wrote:
> I don't see what you're talking about? None of your February emails
> were sent to ozlabs according to the archives there. Threads for the
> bitcoin-dev mailing list are stored here:
>
On Sat, Feb 13, 2021 at 4:18 AM Luke Kenneth Casson Leighton
wrote:
> ... actually i don't see them in the bounces. what's happening there?
>
> On Saturday, February 13, 2021, Luke Kenneth Casson Leighton <
> l...@lkcl.net> wrote:
> > On Sat, Feb 13, 2021 at 6:10 AM ZmnSCPxj
> wrote:
> >> Good
On Sat, Feb 13, 2021 at 6:10 AM ZmnSCPxj wrote:
>
> Good morning Luke,
morning - can i ask you a favour because moderated (off-topic)
messages are being forwarded
https://lists.ozlabs.org/pipermail/bitcoin-dev-moderation/
could you send these instead to libre-soc-...@lists.libre-soc.org?
many
Good morning Luke,
Another thing we can do with scan mode would be something like the below
masking:
input CLK, RESET_N;
input TESTMODE;
input SCANOUT_INTERNAL;
output SCANOUT_PAD;
reg gating;
wire n_gating = gating && TESTMODE;
always_ff @(posedge CLK, negedge
Good morning Luke,
> > (to be fair, there were tools to force you to improve coverage by injecting
> > faults to your RTL, e.g. it would virtually flip an `&&` to an `||` and if
> > none of your tests signaled an error it would complain that your test
> > coverage sucked.)
>
> nice!
It
On Wednesday, February 3, 2021, ZmnSCPxj wrote:
> Good morning again Luke,
:)
> If you mean miner power usage, then power efficiency will not reduce
energy consumption.
> Thus, any rational miner will just pack more miners in the same number of
watts rather than reduce their watt consumption.
(hi folks do cc me, i am subscribed digest, thank you for doing that,
ZmnSCPxj)
On Wednesday, February 3, 2021, ZmnSCPxj wrote:
> Good morning Luke,
>
> I happen to have experience designing digital ASICs, mostly pipelined
data processing.
> However my experience is limited to larger geometries
Good morning again Luke,
> [my personal favourite is a focus on power-efficiency: battery-operated
> hand-held devices at or below 3.5 watts (thus not requiring thermal pipes or
> fans - which tend to break). i have to admit i am a little alarmed at the
> world-wide energy consumption of
Good morning Luke,
I happen to have experience designing digital ASICs, mostly pipelined data
processing.
However my experience is limited to larger geometries and in SystemVerilog.
On the technical side, as I understand it (I have been out of that industry for
4 years now, so my knowledge may
folks, hi, please do cc me as i am subscribed "digest", apologies for the
inconvenience.
i've been speaking on and off with kanzure, asking his advice about a libre
/ transparently-developed ASIC / SoC, for some time, since meeting a very
interesting person at the Barcelona RISC-V Workshop in
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