[Bug gprofng/29663] gprofng fails to find libgp-collector.so

https://sourceware.org/bugzilla/show_bug.cgi?id=29663 Vladimir Mezentsev changed: What|Removed |Added Resolution|--- |FIXED

[Bug ld/29748] v850 linker always triggers LOAD segment with RWX permissions test by default

https://sourceware.org/bugzilla/show_bug.cgi?id=29748 --- Comment #3 from Mike Frysinger --- thanks, that fixed it for --target=v850-elf & --target=all for me -- You are receiving this mail because: You are on the CC list for the bug.

[Bug binutils/29737] strip: section attributes to indicate strip or persistent sections

https://sourceware.org/bugzilla/show_bug.cgi?id=29737 --- Comment #6 from Guillermo E. Martinez --- (In reply to Nick Clifton from comment #5) > (In reply to Guillermo E. Martinez from comment #4) > Hi Guillermo, > Hi Nick, > > > Are you asking for strip to be able to keep or remove sections

[Bug ld/29748] v850 linker always triggers LOAD segment with RWX permissions test by default

https://sourceware.org/bugzilla/show_bug.cgi?id=29748 --- Comment #2 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Nick Clifton : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=e26943f9c7285a453c5daf10ed078b2a014977c6 commit

[Bug ld/29748] v850 linker always triggers LOAD segment with RWX permissions test by default

https://sourceware.org/bugzilla/show_bug.cgi?id=29748 Nick Clifton changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

https://sourceware.org/bugzilla/show_bug.cgi?id=25202 Nick Clifton changed: What|Removed |Added Attachment #14432|0 |1 is obsolete|

[Bug ld/29748] New: v850 linker always triggers LOAD segment with RWX permissions test by default

https://sourceware.org/bugzilla/show_bug.cgi?id=29748 Bug ID: 29748 Summary: v850 linker always triggers LOAD segment with RWX permissions test by default Product: binutils Version: unspecified Status: NEW

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

https://sourceware.org/bugzilla/show_bug.cgi?id=25202 Nick Clifton changed: What|Removed |Added Status|ASSIGNED|WAITING -- You are receiving this

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #6 from Nick Clifton --- Created attachment 14432 --> https://sourceware.org/bugzilla/attachment.cgi?id=14432=edit Proposed patch Please can somebody try out this patch ? It *might* work, but all this endian-ness stuff is

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

https://sourceware.org/bugzilla/show_bug.cgi?id=25202 Nick Clifton changed: What|Removed |Added Ever confirmed|0 |1 CC|

[Bug ld/29741] AVR ld unable to link for 0-series MCUs

https://sourceware.org/bugzilla/show_bug.cgi?id=29741 --- Comment #5 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Nick Clifton : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=78cd9188d0fb3ab8b1c33b4cb54ad85ffa444192 commit

[Bug ld/29741] AVR ld unable to link for 0-series MCUs

https://sourceware.org/bugzilla/show_bug.cgi?id=29741 Nick Clifton changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED