[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2022-09-05 Thread nelsonc1225 at sourceware dot org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org --- C

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-19 Thread liuyingying19 at huawei dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #5 from GraceLiu --- (In reply to Jim Wilson from comment #4) > Yes, I'd call this a compiler bug. It is triggered when we have a long long > inside a packed structure compiled for a 32-bit target, where the long long > must be pa

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-19 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #4 from Jim Wilson --- Yes, I'd call this a compiler bug. It is triggered when we have a long long inside a packed structure compiled for a 32-bit target, where the long long must be partially contained in the first word of the st

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-18 Thread liuyingying19 at huawei dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #3 from GraceLiu --- (In reply to Jim Wilson from comment #1) > The medany explicit-relocs problem is different than the one here. This > requires an auipc to trigger, and there is no auipc here. > > This looks like a compiler bu

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #2 from Jim Wilson --- Another possibility here is a broken linker script that isn't respecting section alignment. -- You are receiving this mail because: You are on the CC list for the bug. __

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment #1