Andy Wingo in IRC pointed out that the reason the patch appears to work
is that the `movr` isn't idempotent! By the time it comes round again,
`val` has already been overwritten by LDAXR in the case that `dst == val`.
On 22/04/2024 10:18, Tony Garnock-Jones wrote:
Oh man. This little patch all
Oh man. This little patch all by itself makes the problem behaviour go
away. No switching to SWPAL/CASAL, just tightening the spinloop. (And no
changes at all to the CAS code, so nothing to do with the fibers bug I
guess.)
With the patch, the spinloop goes LDAXR-STLXR-CBNZ (which is what GCC
As an alternative to changing the JIT to produce SWPAL/CASAL, because I
wasn't sure if *all* aarch64 targets support these, I tried adding DMB
ISH or DMB SY to the end of the generated code sequences. Surprisingly,
this did not fix the issue! So there's perhaps something fishy about the
LDAXR-S
