Regarding compilation error.

2007-11-28 Thread Nisha G
Dear Sir/Madam When compiling with make I'm getting an error as below. I have also copied and pasted the makefile below the error generated.

Re: Regarding compilation error.

2007-11-28 Thread Paul Smith
On Wed, 2007-11-28 at 12:17 +0530, Nisha G wrote: When compiling with make I'm getting an error as below. This is a bug in your code, not a bug in GNU make. We can't help you solve bugs in your code: this mailing list is for bugs in the GNU make program itself. Good luck! --

[bug #21661] Make expands command-line variable defnitions after/during every command invocation

2007-11-28 Thread Robert Bogomip
URL: http://savannah.gnu.org/bugs/?21661 Summary: Make expands command-line variable defnitions after/during every command invocation Project: make Submitted by: bobbogo Submitted on: Wednesday 28/11/07 at 16:43

[bug #21661] Make expands command-line variable defnitions after/during every command invocation

2007-11-28 Thread Dave Korn
Follow-up Comment #1, bug #21661 (project make): As far as I can see, this is the expected and as-intended behaviour. Try make 'var:=$(warning hello)' instead, and refresh your memory on the difference between immediate and deferred expansion.

[bug #21661] Make expands command-line variable defnitions after/during every command invocation

2007-11-28 Thread Robert Bogomip
Follow-up Comment #2, bug #21661 (project make): I set $var on the command-line. Note that it is not mentioned _anywhere_ inside the Makefile, and yet it (or its expression) seems to be being expanded whenever the Makefile runs a command --- _any_ and _all_ commands. Expected behaviour?

[bug #21661] Make expands command-line variable defnitions after/during every command invocation

2007-11-28 Thread Paul D. Smith
Follow-up Comment #5, bug #21661 (project make): Ah, now it's clear what the confusion is. This happens because make puts command line variable settings into the environment to be exported to the subshell. And, of course, before make can invoke a subshell it has to expand all the variables

canonicalization/stripping of leading ./

2007-11-28 Thread dherring
Here's an example makefile: cat _EOF Makefile test.out: ./script.sh $ $@ _EOF Now when I run make, it executes `script.sh test.out` instead of `./script.sh test.out` This is all fine when 'PATH=.:stuff', and sometimes acceptable when 'PATH=stuff:.'; but in the general case, its

RE: canonicalization/stripping of leading ./

2007-11-28 Thread Martin Dorey
http://www.gnu.org/software/make/manual/make.html#Makefile-Basics suggests you follow your final suggestion, as you (seem to) have a $(srcdir) variable. It suggests ./ otherwise, although I've tripped over doing that and generally use $(CURDIR)/ myself. It's helpful elsewhere that ./file and

RE: canonicalization/stripping of leading ./

2007-11-28 Thread dherring
On Wed, 28 Nov 2007, Martin Dorey wrote: http://www.gnu.org/software/make/manual/make.html#Makefile-Basics suggests you follow your final suggestion, as you (seem to) have a $(srcdir) variable. It suggests ./ otherwise, although I've tripped over doing that and generally use $(CURDIR)/ myself.