I'm trying the following Makefile for building an executable from a .c
source file:
: .SUFFIXES: .o .c
: .PRECIOUS: %.o
:
: % : %.c
: .o:
: echo linking
: .c.o:
: echo compiling
This works like it should, for example
$ touch foo.c
$ make -n foo
echo compiling
echo linking
I wrote:
> For a long time, using $(srcdir) in targets and prerequisites in
> Makefiles have seemed a little magic to me. It breaks too often,
> usually in ways like automatic dependency generation not working.
Ooops, I sent this mail too early, before getting to the conclusion.
Anyway, I think m
For a long time, using $(srcdir) in targets and prerequisites in
Makefiles have seemed a little magic to me. It breaks too often,
usually in ways like automatic dependency generation not working.
So I've tried to create a small toy project, and a testscript that
builds the projects in various ways
