Follow-up Comment #6, bug #21661 (project make):
Aha, that explains everything. You are right of course, it's not a regression
(as I found out after digging out 3.79.1 and 3.80), so appologgies for any
aspersions cast.
Using something like ~ for the variable name on the cammand line is a
decent
URL:
http://savannah.gnu.org/bugs/?21661
Summary: Make expands command-line variable defnitions
after/during every command invocation
Project: make
Submitted by: bobbogo
Submitted on: Wednesday 28/11/07 at 16:43
Follow-up Comment #1, bug #21661 (project make):
As far as I can see, this is the expected and as-intended behaviour. Try
make 'var:=$(warning hello)'
instead, and refresh your memory on the difference between immediate and
deferred expansion.
Follow-up Comment #2, bug #21661 (project make):
I set $var on the command-line. Note that it is not mentioned _anywhere_
inside the Makefile, and yet it (or its expression) seems to be being expanded
whenever the Makefile runs a command --- _any_ and _all_ commands.
Expected behaviour?
Follow-up Comment #5, bug #21661 (project make):
Ah, now it's clear what the confusion is. This happens because make puts
command line variable settings into the environment to be exported to the
subshell. And, of course, before make can invoke a subshell it has to expand
all the variables
