Re: RFR: 8199138: Add RISC-V support to Zero

Looks still good. ..Thomas On Tue 7. Apr 2020 at 01:20, John Paul Adrian Glaubitz < glaub...@physik.fu-berlin.de> wrote: > Hello! > > On 4/6/20 8:09 PM, John Paul Adrian Glaubitz wrote: > > I have reduced the complexity of the patch as some of the changes from > > the previous change set are not

Re: RFR: 8199138: Add RISC-V support to Zero

Hello! On 4/6/20 8:09 PM, John Paul Adrian Glaubitz wrote: > I have reduced the complexity of the patch as some of the changes from > the previous change set are not necessary, in particular the changes > to config.{guess,sub}, the definition of EM_RISCV (which is already defined > by the Linux ke

Re: RFR: 8199138: Add RISC-V support to Zero

Hi Adrian, looks good to me. Cheers, Thomas On Mon, Apr 6, 2020, 20:11 John Paul Adrian Glaubitz < glaub...@physik.fu-berlin.de> wrote: > Hello! > > Please review this small change which adds basic support for the riscv64 > target for Linux/Zero [1]. > > I have reduced the complexity of the patc

Re: RFR: 8199138: Add RISC-V support to Zero

Build change looks good. /Erik On 2020-04-06 11:09, John Paul Adrian Glaubitz wrote: Hello! Please review this small change which adds basic support for the riscv64 target for Linux/Zero [1]. I have reduced the complexity of the patch as some of the changes from the previous change set are no

RFR: 8199138: Add RISC-V support to Zero

Hello! Please review this small change which adds basic support for the riscv64 target for Linux/Zero [1]. I have reduced the complexity of the patch as some of the changes from the previous change set are not necessary, in particular the changes to config.{guess,sub}, the definition of EM_RISCV

Re: RFR: 8199138: Add RISC-V support to Zero

Hi Aleksey! On 2/17/20 9:07 AM, Aleksey Shipilev wrote: > On 2/12/20 6:13 PM, Aleksey Shipilev wrote: >> On 2/12/20 6:00 PM, John Paul Adrian Glaubitz wrote: >>> On 2/12/20 5:59 PM, Aleksey Shipilev wrote: On 2/12/20 5:54 PM, John Paul Adrian Glaubitz wrote: > I assume I can push with tho

Re: RFR: 8199138: Add RISC-V support to Zero

On 2/12/20 6:13 PM, Aleksey Shipilev wrote: > On 2/12/20 6:00 PM, John Paul Adrian Glaubitz wrote: >> On 2/12/20 5:59 PM, Aleksey Shipilev wrote: >>> On 2/12/20 5:54 PM, John Paul Adrian Glaubitz wrote: I assume I can push with those changes and mark it as Reviewed-by: erikj, shade? >>>

Re: RFR: 8199138: Add RISC-V support to Zero

This seems fine to me too. Thanks, David On 13/02/2020 3:08 am, John Paul Adrian Glaubitz wrote: Hi! On 2/12/20 5:51 PM, Aleksey Shipilev wrote: Neat. Looks good to me. Minor nits in os_linux.cpp: *) Can you move the comment to the #define line, as it is done in the similar blocks in the s

Re: RFR: 8199138: Add RISC-V support to Zero

On 2/12/20 6:00 PM, John Paul Adrian Glaubitz wrote: > On 2/12/20 5:59 PM, Aleksey Shipilev wrote: >> On 2/12/20 5:54 PM, John Paul Adrian Glaubitz wrote: >>> I assume I can push with those changes and mark it as Reviewed-by: erikj, >>> shade? >> >> Mark it, yes. I believe non-trivial (yet exceedi

Re: RFR: 8199138: Add RISC-V support to Zero

Hi! On 2/12/20 5:51 PM, Aleksey Shipilev wrote: > Neat. Looks good to me. > > Minor nits in os_linux.cpp: > > *) Can you move the comment to the #define line, as it is done in the similar > blocks in the same file? > > 1854 #ifndef EM_RISCV /* RISCV */ > 1855 #define

Re: RFR: 8199138: Add RISC-V support to Zero

On 2/12/20 5:59 PM, Aleksey Shipilev wrote: > On 2/12/20 5:54 PM, John Paul Adrian Glaubitz wrote: >> I assume I can push with those changes and mark it as Reviewed-by: erikj, >> shade? > > Mark it, yes. I believe non-trivial (yet exceedingly simple) things like > these require waiting for > 24

Re: RFR: 8199138: Add RISC-V support to Zero

On 2/12/20 5:54 PM, John Paul Adrian Glaubitz wrote: > I assume I can push with those changes and mark it as Reviewed-by: erikj, > shade? Mark it, yes. I believe non-trivial (yet exceedingly simple) things like these require waiting for 24 hours to anyone else to chime in with comments. There se

Re: RFR: 8199138: Add RISC-V support to Zero

Hi! On 2/12/20 5:51 PM, Aleksey Shipilev wrote: > On 2/12/20 5:14 PM, John Paul Adrian Glaubitz wrote: >>> [1] http://cr.openjdk.java.net/~glaubitz/8199138/webrev.00/ > > Neat. Looks good to me. > > Minor nits in os_linux.cpp: > > *) Can you move the comment to the #define line, as it is done i

Re: RFR: 8199138: Add RISC-V support to Zero

On 2/12/20 5:14 PM, John Paul Adrian Glaubitz wrote: >> [1] http://cr.openjdk.java.net/~glaubitz/8199138/webrev.00/ Neat. Looks good to me. Minor nits in os_linux.cpp: *) Can you move the comment to the #define line, as it is done in the similar blocks in the same file? 1854 #ifndef EM_RISCV

Re: RFR: 8199138: Add RISC-V support to Zero

Build changes look ok to me. Someone from hotspot should review the cpp file. /Erik On 2020-02-12 08:14, John Paul Adrian Glaubitz wrote: Hi! This is an updated RFR to add basic RISC-V support to Zero. This patch is being used for the riscv64 port in Debian. Please review the changes in [1]

RFR: 8199138: Add RISC-V support to Zero

Hi! This is an updated RFR to add basic RISC-V support to Zero. This patch is being used for the riscv64 port in Debian. Please review the changes in [1]. Thanks, Adrian > [1] http://cr.openjdk.java.net/~glaubitz/8199138/webrev.00/ -- .''`. John Paul Adrian Glaubitz : :' : Debian Develope

Re: RFR: 8199138: Add RISC-V support to Zero

On Tue, 2018-03-27 at 17:46 +0900, John Paul Adrian Glaubitz wrote: > On 03/27/2018 05:23 PM, Edward Nevill wrote: > > Sorry for the delay. I was doing another test build on qemu which takes > > about 3 days. > > > > > What confuses me: Why RISCV here and not RISCV64? > > In particular this hun

Re: RFR: 8199138: Add RISC-V support to Zero

On Tue, 2018-03-27 at 17:46 +0900, John Paul Adrian Glaubitz wrote: > On 03/27/2018 05:23 PM, Edward Nevill wrote: > > @@ -1733,6 +1733,9 @@ > > #ifndef EM_AARCH64 > >#define EM_AARCH64183 /* ARM AARCH64 */ > > #endif > > +#ifndef EM_RISCV /* RISCV *

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/27/2018 05:23 PM, Edward Nevill wrote: > Sorry for the delay. I was doing another test build on qemu which takes about > 3 days. > > Please review the following webrev > > http://cr.openjdk.java.net/~enevill/8199138/webrev.02 > > This has the following additional changes over the previous

Re: RFR: 8199138: Add RISC-V support to Zero

Hi, On Tue, 2018-03-27 at 14:10 +0900, John Paul Adrian Glaubitz wrote: > On 03/24/2018 02:26 AM, Magnus Ihse Bursie wrote: > > > > On 2018-03-20 14:54, Edward Nevill wrote: > > > Thanks for this. I have updated the webrev with the above comment. > > > > > > http://cr.openjdk.java.net/~enevill/8

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/24/2018 02:26 AM, Magnus Ihse Bursie wrote: > > On 2018-03-20 14:54, Edward Nevill wrote: >> Thanks for this. I have updated the webrev with the above comment. >> >> http://cr.openjdk.java.net/~enevill/8199138/webrev.01 > I note that in platform.m4 (sorry I didn't say this earlier), you set

Re: RFR: 8199138: Add RISC-V support to Zero

On 2018-03-20 14:54, Edward Nevill wrote: On Tue, 2018-03-20 at 08:39 +0100, Erik Helin wrote: Please review the following webrev Bugid: https://bugs.openjdk.java.net/browse/JDK-8199138 Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 32 # First, filter out everything that do

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/20/2018 02:54 PM, Edward Nevill wrote: On Tue, 2018-03-20 at 08:39 +0100, Erik Helin wrote: Please review the following webrev Bugid: https://bugs.openjdk.java.net/browse/JDK-8199138 Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 32 # First, filter out everything tha

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/19/2018 05:19 AM, Edward Nevill wrote: > Interestingly, there is no implementation of atomic_copy64 for ARM32. I guess > it just relies on the compiler generating LDRD/STRD correctly and doesn't > support earlier ARM32 archs. I'll do a bit of investigation. I am planning to add arch-speci

Re: RFR: 8199138: Add RISC-V support to Zero

On Tue, 2018-03-20 at 08:39 +0100, Erik Helin wrote: > Please review the following webrev > > > > Bugid: https://bugs.openjdk.java.net/browse/JDK-8199138 > > Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 > >32 # First, filter out everything that doesn't begin with "aarch64-" >

Re: RFR: 8199138: Add RISC-V support to Zero

Build changes look ok to me. /Erik On 2018-03-17 12:02, Edward Nevill wrote: Hi, Please review the following webrev Bugid: https://bugs.openjdk.java.net/browse/JDK-8199138 Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 This webrev add Zero support for RISC-V I propose to set

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/18/2018 08:19 PM, Edward Nevill wrote: > Pretty much. The only atomic operation which doesn't used GCC builtins is > os::atomic_copy64. For RISC-V this just does the same as all other 64 bit > CPUs. > > *(jlong *) dst = *(const jlong *) src; That's probably wrong, but it'll do for now

Re: RFR: 8199138: Add RISC-V support to Zero

On Sun, 2018-03-18 at 14:37 +, Andrew Haley wrote: > On 03/17/2018 07:02 PM, Edward Nevill wrote: > > Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 > > > > This webrev add Zero support for RISC-V > > What happens with atomics? Do we fall back to GCC builtins for everything? >

Re: RFR: 8199138: Add RISC-V support to Zero

On 03/17/2018 07:02 PM, Edward Nevill wrote: > Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 > > This webrev add Zero support for RISC-V What happens with atomics? Do we fall back to GCC builtins for everything? -- Andrew Haley Java Platform Lead Engineer Red Hat UK Ltd.

RFR: 8199138: Add RISC-V support to Zero

Hi, Please review the following webrev Bugid: https://bugs.openjdk.java.net/browse/JDK-8199138 Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 This webrev add Zero support for RISC-V I propose to set up a project to develop template interpreter, C1 & C2 support for RISC-V and I wi