hi wan,
sync should be zero on every clock except
it should go high for one clock every N cycles,
where N is in henry chen's memo on sync pulses.
for example simulink spectrometer designs and
examples on how to use sync pulse,
see design gallery at:
http://casper.berkeley.edu/design_gallery.p
Hi Wanxiang,
If the sync you're setting is the simulation input to the ADC block,
then it's treated as the reset to your sync generator, not the sync
itself. In this case, when you set it to 1 you're just always holding
down the reset to your counter, so you're actually never generating
your sync
Hi Andrew:
Another strange thing is I still get the output no matter I set Sync to "0" or
"1". I think Sync could be considered as a sync reset signal. I should not get
anything out if I fix the sync to "1".
Wan
From: Andrew Martens [mailto:martens.and...@gmail
Hi Andrew:
Thanks. I change the sync period. But it looks still wrong. I put the modified
mdl file again. Anybody could find something wrong?
The attached are the mdl file and the output wave.
Thanks
Wan
From: Andrew Martens [mailto:martens.and...@gmail.com]
S
Hi Wan
Also remember that you have a PFB so (from the memo) you should remember to
include the number of taps in your calculation.
e.g 2 order-2 reorder blocks, order-9 unscrambler, 4 input, 2048 channels, 2
tap PFB
min sync = 2x(2x9x2048/4) = 9216x2
Good luck
Andrew
2008/11/5
> Hi Andrew:
5 matches
Mail list logo
