Re: [casper] Timing error

Hi John Some pointers on improving timing generally in ROACH. Decrease the space your design occupies. Implement delays on data inputs to multiplier cores in behavioural logic as these are absorbed by the DSP48E core. Implement large adders and counters in DSP48Es. Use Truncation as your Roundin

Re: [casper] ROACH hangs before Uboot prompt

Hi again Jason, thanks again. Swapping to the FPGA dimm did indeed get me to the uboot prompt (although with the same memory errormessages along the way). However I have not been able to then proceed to boot the kernel, but this may be because I now have no memory available to the FPGA. It ma

Re: [casper] Timing error

> > On Nov 12, 2009, at 16:36 , John Ford wrote: > >> At least one timing constraint is impossible to meet because >> component delays alone exceed the constraint. > > I think this means that part of your design synthesized to multiple > levels of combinatorial logic where the sum of each level's c

Re: [casper] Timing error

On Nov 12, 2009, at 16:36 , John Ford wrote: At least one timing constraint is impossible to meet because component delays alone exceed the constraint. I think this means that part of your design synthesized to multiple levels of combinatorial logic where the sum of each level's component

[casper] Timing error

Hi all. Can you give me a hint on these 2 fatal errors? The NCD file is too big to attach. John foo Description: Binary data

Re: [casper] Capser FFT output level with Matlab FFT output level

Hi Andrew: Thanks. Your answer is very clear and solve my problem. I should divide it by 2^9 to get right power level. And I still could not understand one thing: The casper fft spectrum output for a single carrier (1 point) looks much narrower than mablab float point fft and fix point fft(3 p

[casper] adc083000 yellow block labeling

hi john, as you suspected, the samples from ADC083000 emerge eight at a time, from a single adc. (not IQ). the yellow block is badly labeled. the yellow block outputs should be labled adc_sample_0 through adc_sample_7. i'm not sure what time order the samples come out in. i think mark an

Re: [casper] Questions on porting to ROACH

Hi Andrew. This was very helpful. It almost worked. :) It all fit in the chip, but it failed to meet timing on the adc0_clk line and the 156 MHz clock line. I've messed about with it some more in an attempt to make it meet timing. John > Hi John > > The FFT is a good place to optimise for var

[casper] ADC083000x2 block

Hi all. I'm looking at using this block, and the documentation doesn't quite match up to the block. I'm using only zdok0. The outputs on the block are labelled adc0_i0,adc0_q0, ... ,adc0_i3,adc0_q3. Are these just demuxed output samples at 1/4 the clock frequency, like on the ADC, or are they s