Re: [casper] OPB address overlap on ROACH

Hi Henry. That was definitely an oversight on my part. > The way I'm reading gen_xps_mod_mhs for the powerpc440_ext is that each > bridge's address space essentially has static allocation using The bridges are currently designed to fit on 0x8 intervals after the 0x100 simulink peripheral

[casper] OPB address overlap on ROACH

Hi Dave, We've just encountered an interesting issue here where the toolflow's bus addresser gives overlapping addresses as it spans two bridges. What seems to be happening is that there are a fairly large number of BRAMs in the design, and so by the time a new opb2opb bridge is inserted, the add

Re: [casper] gpu PFB

Thanks, Its a nicely written document. Answers all the PFB questions I've never had time to look into. Glen > Hi Simon and Terry, > > Concerning a gpu implementation of a PFB, the following/attached > is additional material. It is from Chris Harris at U. Western Aus. > > Best, > > Lincoln > > -

[casper] ppc440epx debugging breakthrough

Hi All. I have been doing some work on reverse engineering the jtag/ocd interface on the ppc440epx (which is a closed protocol). Turns out I've had a bit of luck. It is now possible to 'debrick' a ROACH board, ie load up a bootloader, without any proprietary tools or programmers. The programmer I