Re: [casper] dual-port shared BRAM

Hi Jay, Unfortunately, the secret sauce of the Shared BRAM yellow block is that it uses the dual-port BRAM under the hood; one port goes to the FPGA fabric, and the other goes to the processor bus. The single-port bram block under the mask is just there to provide a simulation model, and doesn't

[casper] dual-port shared BRAM

I'm working on a project that currently uses a dual-port BRAM (generated from Coregen) in a VHDL black-box. I would like to port the address/data signals outside of the box and use a shared BRAM yellow block so I can read and write from ipython, but sadly the yellow block is only single porte

[casper] confirm DAFIRv9_0 does not work with ROACH 1?

Hey Casperites, I've been recently working on a design that uses a DAFIRv9.0 from the 11.5 Xilinx toolset, and the simulated behavior and on-chip behavior are very different. Checking the manual, I see that it does not seem to be valid for the Virtex 5 chip in the Roach 1. Can anyone confirm thi

Re: [casper] NFS boot failure

Thank you Alec. Just as you said, I unzip the file system with root permission, it works now. Best Regards Renjie -原始邮件- 发件人: "Alec Rust" 发送时间: 2012年6月29日 星期五 收件人: zh...@shao.ac.cn 抄送: casper 主题: Re: [casper] NFS boot failure It would seem that your root file system is not loading

Re: [casper] KatADC documentation and questions

Hi Luis I am copying to the casper list as others may find this useful. > I wonder where are the en0/1 and atten0/1 signals for the katADC? I > tried to find it in the Verilog code (e.g. gain_set.v in I2C controller > pacore) or schematics, and I can not see any reference. The only thing > tha