Hi, Andrea, On Apr 4, 2013, at 2:20 AM, Andrea Mattana wrote:
> I have updated to the latest mlib_devel, and installed the 14.4. I > cannot run the simulation because my MATLAB 8.0 doesn't have yet the > DSP Toolbox needed for the downsampler into the iADC block, anyway I > found a difference with the past version, the actual ADC block takes > in input just three simulation signals rather than four. I have posted > the new screenshot on http://www.med.ira.inaf.it/~mattana/casper/ . The new screenshot looks like the mask initialization failed (probably due to the dspsigops/downsample block problem). The iADC (named just "adc" since that was the first CASPER ADC board) block has three simulation inputs when running in "ADC interleave mode" and four simulation inputs when NOT in "ADC interleave mode". The fact that your new screenshot shows three simulation inputs makes me think the adc block is in interleave mode, but when in ADC interleave mode, the first (topmost) eight outputs of the adc block are labeled "o0" through "o7" yet your new screenshot shows them as "i0" to "i3" and "q0" to "q3". I think this is inconsistency implies that the mask initialization script failed. > Do you think I will be able to simulate/compiling it replacing the > downsampler block using the simulink downsampler without having > installed the DSP Toolbox?! (I need to check to the mail archive > because somebody has notified me some weeks ago). Are you sure the Signal Processing Toolbox is missing the downsample block? I don't have 14.4 so I can't check. At some point the downsample block changed so that it no longer works with the mask initialization script. I hope to push a fix for that soon. AFAIK, the only other downsample block is the Xilinx one and that will not work unless maybe if you also include "gateway in" and "gateaway out" blocks around it (but I don't recommend that). Based on your old screen shot I think I know why the design didn't work. The adc simulation inputs have a sample time of 0.25 (or 0.125 in ADC interleave mode). The adc block's outputs have a sample time of 1. This simulates the demux-by-four (or demux-by-eight in interleave mode) that the ADC chip provides. For better or worse (i.e. I don't think it's really necessary but I didn't write the adc yellow block), the sync signal is sampled in the FPGA four times per clock cycle and this over sampled version is also demuxed by four (even in interleave mode). My guess is that the pulse generator driving the sim_sync input is high for one sample at the 0.25 sample time, but that the 0.25 interval that it is high gets demuxed to one of the sync outputs that are not connected to anything. If you add the 4 input OR gate to the first design, I think it will work as you expect. Hope this helps, Dave
