Re: [casper] Simulink Input output problem.

Hi Nishanth Hi All, I have a basic doubt after I installed simulink and Xilinx according to the Casper website I find that In the casper DSP blocks has NO INPUTS and OUTPUTS connected to it (green blocks- the downconverters mixers) .The blocks in yellow are all fine and has inputs and ou

[casper] Simulink Input output problem.

Hi All, I have a basic doubt after I installed simulink and Xilinx according to the Casper website I find that In the casper DSP blocks has NO INPUTS and OUTPUTS connected to it (green blocks- the downconverters mixers) .The blocks in yellow are all fine and has inputs and outputs. Is there a

Re: [casper] Simple clk divider

Thanks Glen - I can see that will work. On Wed, Nov 13, 2013 at 2:41 PM, G Jones wrote: > Usually people just slice the bit you want off a counter. To select > the bit using a software register, just use the software register as > the select for a mux. Or use the software register as a bit mask a

Re: [casper] Simple clk divider

Usually people just slice the bit you want off a counter. To select the bit using a software register, just use the software register as the select for a mux. Or use the software register as a bit mask and AND it with the counter, then use the output of a relational == 0 as your divided counter. O

[casper] Simple clk divider

Hi All, I suspect this is really simple but I just cannot get this to work in simulink. I would like to divide the sys_clk by a factor set by a software register. To do this in VHDL is very simple - You setup a counter and invert the output when it reaches half of the required clk divide - the c