Hi Dave,
I just had some time to investigate your comment, and run the script you
linked to, and indeed there may be some problem here. The output of the
script is shown below, which seems to indicate that all of the NICs are
connected to cpus 0-7 (socket 0). We steered the interrupts (47 and
Hi Peix Xin,
That should work. What mlib_devel are you using?
Is your ADC card a demux 1 version?
What ADC yellow block settings?
What snap MSSGE block settings (should be clocking from adc0_clk)
Are you applying a clock to the ADC card - you can't use the on-board
synthesiser with an external
Hi Jack,
We want use ADC5G card on SNAP board, is there any setting to switch on ZDOK
connector?
The programming is done, however, it returnned 0.0 when we try
fpga.est_brd_clk() to check the FPGA's clock.
Best wishes,
Pei Xin
==
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