RE: [casper] System Verilog

Sorry, I missed the rest of a comment: >> there is “standard” way of doing things … The Mentor way, the Cadence way, the Aldec way, … you get the drift. Mentor’s Verification Academy has a lot of good resources for learning SystemVerilog, UVM, Code Coverage. On the subject of Code Coverage,

RE: [casper] System Verilog

Hi All, Cliff Cummings still does training. We have had him come to JPL to give classes in UVM. He has a good teaching style. I have his contact details if anyone is interested. (His company is now part of Paradigm-Works, another company I have used). Once you dig into UVM, you’ll find that

Re: [casper] System Verilog

If you are still looking and can afford to pay for a pro trainer check out: http://www.sunburst-design.com His website is a little out of date but if Cliff Cummings is still training he has a complete course and he has trained hundreds of people. Cliff may have something you can tag along on

[casper] Re: System Verilog

Hey Jack, A little late here but better late than never I suppose... Papers worth a read: - https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf - http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf -