The following file appears to be the beginnings of a hardware testing flow for AXI-Lite interface, in the spirit of the JTAG-to-AXI-Master IP. It seems to be missing some key components (yellow blocks and .m mask).
https://github.com/casper-astro/mlib_devel/blob/m2021a/jasper_library/hdl_sources/jtag_axil_master/jtag_axil_master_fpg_to_tcl.py What is the current status of this portion of the codebase? -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/930ea906-5e15-4571-92be-5732148945ffn%40lists.berkeley.edu.
