Hi All,

To hopefully save anyone going through the same pain, this behaviour only
occurs when using the AD9082 in ADC-only (i.e. JESD TX only) mode, and it
turns out that in this mode one still has to set the DAC JESD Receiver
(0x4AE, for anyone from the future reading this) to JESD204C mode even if
the receiver isn't being used.

It looks like this was fixed in the ADI linux drivers a while back, but
alas not in the version I was using.

Thanks to everyone who reached out with suggestions / commiserations.

Cheers
Jack


On Sat, 24 Feb 2024 at 17:30, Jack Hickish <jackhick...@gmail.com> wrote:

> Hi casperites,
>
> I'm hoping someone can help me out of a JESD204C subclass 1
> synchronization hell. There is a long version of this story, but the short
> version is:
>
> 1. I have an AD9082-FMCA-EBZ development board (hosting an AD9082 ADC+DAC
> chip) being used with an iWave ZU11 development board.
> 2. I'm following ADI's user guide (and API) to command a one-time
> synchronization of the JESD LEMC clock to an externally supplied SYSREF
> clock.
> 3. Each time I command a one-time synchronization event, I see the
> relationship of the LEMC and SYSREF change by 32 samples (and once changed
> it remains consistent), but the phasing is never zero, which is the entire
> point of the synchronization process.
>
> There are a few bits of suspiciousness afoot -- for example, if I power
> down the SYSREF receiver on the ADC I see that the relationship of the LEMC
> and SYSREF doesn't change between synchronization requests, but, I also
> always see the ONESHOT_SYNC_DONE register indicate synchronization has
> completed.
> If I write 0 to the SPI_SYSREF_EN register, that doesn't seem to affect
> anything at all?!
>
> I'm about to write a long post to the ADI forums, but if anyone has any
> familiarity with this ADC family and has time to spare to chat I would be
> forever in your debt.
>
> Cheers
> Jack
>

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