Hi Ken,
In this case, ‘A’ is the name given to the clock constraint.
‘B’ is the net/pin name where this constraint is applied to. Please not that,
in the design there should be a pin with the name ‘B’ in the current module.
Depending on the tool you are using for verification, the TCL command
‘get_pins’ returns the hierarchical representation of the pin ‘B’.
In your case, the constructor would look like below.
CC = ClockConstraint( signal=”<top_module.leaf_module.B>”, name=”A” , freq=None
, period=3.000, port_en=False, virtual_en=False, waveform_min=0.000 ,
waveform_max=1.500)
Or
CC = ClockConstraint( signal=”B”, name=”A” , freq=None , period=3.000,
port_en=False, virtual_en=False, waveform_min=0.000 , waveform_max=1.500)
Hope this helps.
From: casper@lists.berkeley.edu <casper@lists.berkeley.edu> on behalf of Ken
Semanov <shapkiqua...@gmail.com>
Date: Friday, 1 March 2024 at 19:39
To: casper@lists.berkeley.edu <casper@lists.berkeley.edu>
Subject: [casper] ClockConstraint arguments order
Note: This message originated from outside the FIU Faculty/Staff email system.
Say the xdc file required this line
create_clock -period 3.000 -name A -waveform {0.000 1.500} -add [get_pins B]
Where would the A and B be placed in the constructor of ClockConstraint?
CC = ClockConstraint( signal=??, name=?? , freq=None , period=3.000,
port_en=False, virtual_en=False, waveform_min=0.000 , waveform_max=1.500)
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