of pins that ROACH are needed are not included in my design.
How could I program the FPGA of ROACH with my bit file?
Thanks,
C-H Cheng
Hello,
On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote:
Hello All
If I want to simulate a design in ISE and generate a bit file to
download to ROACH over JTAG.
You can
in the input of ISERDES.
Any idea?
Regards,
C-H Cheng
- Errors in physical DRC.
---
I also find some information about this error.
http://www.xilinx.com/support/answers/31620.htm
Should I fix the UCF file? or other idea?
Regards,
C-H Cheng
.
I use the uboot : 20090811-uboot-nohack
kernel : uImage-rmon-20090904
filesystems: ROACH_filesystem_etch_2009_08_14
Also the telnet in ROACH setup OK and I can telnet to ROACH. (port 23, and 7147
are opened in ROACH)
Any idea?
Regards,
C-H
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