[casper] ZCU111 100GbE Example Available Now

f you have any questions! Best, Jenny Smith -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this

Re: [casper] Wideband FFT using Xilinx blocks as primitives

Hi all, Sorry for the late follow-up. I wanted to add to Jeb's comment: The FFT we are using on the RFSoC is 16x4096 meaning it processes 16 complex samples each clock and runs at 512 MHz. We used the Xilinx SSR FFT available in System Generator versions 2019.1+. It can be configured for a differ