On Mon, Jun 1, 2020 at 12:05 PM Marc wrote:
> On Sun, May 31, 2020 at 6:54 PM Wesley New wrote:
>
>
> > You should have tcpborphserver installed on the PS. You can telnet into
> tcpborphserver and issue register read and writes that way. ie you could
> telnet into tcpborphserver on localhost
's petaLinux or something else? Reading the TcpBorphServer
> docs it looks like anything with an appropriate kernel with Zynq drivers
> should work but I'd rather start as close as possible to what other Casper
> people are doing.
>
> Regards,
>
> David
> On 1/14/20 10:21 PM, Ve
Hi David,
You should build the TCPBorphServer code on the Red Pitaya as the code uses
pre-defined compiler macros in order to figure out which architecture
you're using.
On Wed, Jan 15, 2020 at 8:06 AM Vereese Van Tonder
wrote:
> Hi David,
>
> The server is TCPBorphServer and you
Hi David,
The server is TCPBorphServer and you can find it in the tcpborphserver3
directory in the katcp directory located here:
https://github.com/ska-sa/katcp.git
TCPBorphServer is the control software for the Red Pitaya. It is a KATCP
server program that listens for KATCP messages on port
Hi Jason,
Here's a link to RP:
https://github.com/casper-astro/casper-hardware/blob/master/FPGA_Hosts/RED_PITAYA/README.md
in the readme there's a top-level specifications section which you'll find
useful.
Here's a link to the katcp spec:
Hi Yunpeng,
You can try "Black Boxing" parts of your design, that you know works.
There's a tutorial on the CASPER wiki here:
https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box
I hope this helps.
On Sun, Jun 4, 2017 at 4:43 AM, 门云鹏 wrote:
> Hi James, Michael, and
Hi Yunpeng,
You can use Xilinx's PlanAead tool to help with the timing errors. You can
place your PFB in a "pblock" which helps with timing. I haven't worked with
this in awhile but there's a tutorial on the CASPER wiki here:
https://casper.berkeley.edu/wiki/Tutorial_PlanAhead
I hope that helps
Hi Everyone,
We currently have two positions open within the Electronics department
at Green Bank.
1) Division Head - Electronics
2) Electronics Engineer III*
***
Please see the link below to apply for, or to obtain more information
about the positions:
If
you're interested, the thesis can be found here:
http://scholar.sun.ac.za/handle/10019.1/71803
I hope you have fun.
Kind Regards,
Vereese van Tonder
On 03/29/2016 11:42 AM, Juan Camilo Guevara Gomez wrote:
Dear all,
Let me introduce myself, my name is Juan Camilo Guevara, I am a Maste
settings as the hardcoded values (with
the exception of CLKOUT5) . I think the MULTIPLY and DIVIDE
parameters are intended to be used for sys_clk, so I'm not sure
how they get set (or passed on) for aux_clk.
Hope this helps,
Dave
On Aug 4, 2015, at 12:13 PM, Vereese Van Tonder
10 matches
Mail list logo