Hi CASPER team,
Thanks to everybody for the suggestions. Finally the problem has been
solved. This a typical error when you have timing error:
“ERROR: 1 constraint not met.
PAR could not meet all timing constraints. A bitstream will not be
generated.”
It can be generated for different delays
Hi CASPER team,
I am working with the iBOB FPGA at 250 MHz and two iADCs at 1000 GHz in a
correlator project.
In the compilation I have a timing error
ERROR: 1 constraint not met.
PAR could not meet all timing
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