Re: [casper] 3 Gs/s adc board demo example

hi jason, we don't have a design to write 3 Gsps ADC data into DRAM, but if it's useful, suraj and billy have a roach designs that write data from a pair of 3 Gsps ADC's to block ram for subsequent readout via borph. best wishes, dan On 9/30/2010 8:10 AM, Jason Ray wrote: At 09:16 PM 9/29

Re: [casper] 3 Gs/s adc board demo example

At 09:16 PM 9/29/2010, Suraj Gowda wrote: At 3 Gs/s, the FPGA clock rate is 187.5 MHz. Is this in range of the DRAM clock? Maybe you could describe what the output is and/or how it's incorrect? It's been a while since I attempted to use that interface. We had a 200 MHz sine wave input to the

Re: [casper] 3 Gs/s adc board demo example

At 3 Gs/s, the FPGA clock rate is 187.5 MHz. Is this in range of the DRAM clock? Maybe you could describe what the output is and/or how it's incorrect? It's been a while since I attempted to use that interface. _Suraj On Sep 29, 2010, at 6:08 PM, John Ford wrote: Hi John, Just to clari

Re: [casper] 3 Gs/s adc board demo example

> Hi John, > > Just to clarify, do you mean 1 board with 16 outputs / cycle at half > the clock rate? I implemented this feature but I wouldn't recommend > using it for serious computation. For operations like FFT, speed is > not as much a problem as the number of simultaneous Yes, that's what I

Re: [casper] 3 Gs/s adc board demo example

Hi John, Just to clarify, do you mean 1 board with 16 outputs / cycle at half the clock rate? I implemented this feature but I wouldn't recommend using it for serious computation. For operations like FFT, speed is not as much a problem as the number of simultaneous inputs. -Suraj On Se

[casper] 3 Gs/s adc board demo example

Hi all. Does anyone have a working example of using the adc083000 adc board in the 2* demultiplexed mode (16 simultaneous outputs). If so, what sampling rate? Thanks! John