> Tough one with existing hardware. I suspect two 3gsps ADC's would have to
> be
> thermally controlled to get the timing problems down.
Maybe so. We may try to experiment with this some over the summer.
> National sell an
> "up-tested" 4gsps version of the 3gsps part - it may improve matters a
Tough one with existing hardware. I suspect two 3gsps ADC's would have to be
thermally controlled to get the timing problems down. National sell an
"up-tested" 4gsps version of the 3gsps part - it may improve matters a bit, but
the ENOB figures for the part are only shown on a graph up to 2GHz an
Thanks for the info, all.
As you might expect, this was not an idle question. I have a need for
this right now. The machine I need to build is:
3 GHz bandwidth (6 GS/s)
1024 channels in the spectrometer
1 polarization
50 millisecond or less accumulations.
1 ROACH board
How should we proceed wit
Yes, I think a parameter is a good idea. Maybe just a radio-box or a
drop-down-selection in the mask. Multiple cores will confuse users
(like everyone gets confused by the multiple FFT blocks) and will
probably become an admin nightmare down the road.
Jason
On 23 Apr 2010, at 07:40, Dan We
hi jason,
perhaps we can have different yellow block cores,
one hardened for people that need high speed input,
one not hardened,
or better yet - a parameter that selects whether the
routing is hardened or not?
dan
On 4/22/2010 10:32 PM, Jason Manley wrote:
suraj is planning on hardening
suraj is planning on hardening the yellow block cores
so that their routing/timing is locked down, independent
of what else is running in the fpga.
Please don't make this the default behaviour. On designs that are
nearly fully packed (99%), you need to be able to twiddle every part
of the de
hi john,
we've brought 6Gsps data into the fpga from
a pair of interleaved adc's, with the fpga running at 375 MHz,
and doing small things with it, like storing samples in a buffer,
or doing a short fft.
but when we add a lot of stuff into the fpga, the fpga no longer
can clock at 375 MHz.
su
Hi John,
I don't think anyone has been able to get a spectrometer working at
the full 3GS/s interleaved yet.
We are able to digitize and plot raw ADC data at full speed. We run
into timing problems when the chip becomes more full, i.e. with an
FFT. One possible solution we are (I am) expl
Hi John,
I don't think anyone has been able to get a spectrometer working at the full
3GS/s interleaved yet. The best Suraj and I have been able to do is about
2.4Gs/s before we start running into serious timing issues. We do have
plans to meet soon with a Xilinx timing expert in the hopes of re
Hi all.
Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC
boards on a ROACH? I seem to recall someone doing something of the sort,
but I don't recall any details.
Thanks for any info!
John
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