Hi casperites, I'm hoping someone can help me out of a JESD204C subclass 1 synchronization hell. There is a long version of this story, but the short version is:
1. I have an AD9082-FMCA-EBZ development board (hosting an AD9082 ADC+DAC chip) being used with an iWave ZU11 development board. 2. I'm following ADI's user guide (and API) to command a one-time synchronization of the JESD LEMC clock to an externally supplied SYSREF clock. 3. Each time I command a one-time synchronization event, I see the relationship of the LEMC and SYSREF change by 32 samples (and once changed it remains consistent), but the phasing is never zero, which is the entire point of the synchronization process. There are a few bits of suspiciousness afoot -- for example, if I power down the SYSREF receiver on the ADC I see that the relationship of the LEMC and SYSREF doesn't change between synchronization requests, but, I also always see the ONESHOT_SYNC_DONE register indicate synchronization has completed. If I write 0 to the SPI_SYSREF_EN register, that doesn't seem to affect anything at all?! I'm about to write a long post to the ADI forums, but if anyone has any familiarity with this ADC family and has time to spare to chat I would be forever in your debt. Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG1GKSmghUk%3DpVatwEn5Gjsk7SGabfM%2BU7jhuRzBt%3DksyK-F1A%40mail.gmail.com.
