Dear all,
does anyone have a BEE2 they would like to sell/rent?
Kris
Hi all.
We're working hard on cleaning up our 800 MHz Coherent Dedispersion pulsar
machine for production. We have it working with 8 GPU machines, and from
64 to 2048 coarse channels.
One problem we have is that with our output FPGA that rearranges the data
and ships it off simultaneously over 4
Hi everyone,
Does anyone have an off-the-shelf solution for a rack-mountable BEE2 case?
Thanks,
Laura
Hi all. Is there any way to get the eeprom contents while the bee2 is
running linux? Like the get_eeprom command, only from a borph linux
shell.
John
All,
As some of you know, Randy and I have been recently working on trying
to get the interchip connections to work properly, utilizing the
packed registers, phase delays, etc to get synchronized data into
FPGA2. We have a question regarding the build times for BEE2 designs
that use these in
Original Message
Subject:BEE2 for sale
Date: Fri, 12 Sep 2008 13:42:04 -0700
From: Ken Lutz
To: Dan Werthimer
CC: Henry Chen
Hi Dan,
If you know of anyone in your community that might be interested there
is an extra BEE2 system available for sale from
Dear all,
apologies for the mass-emailing, but we are looking to buy a couple of BEE2
boards for a Square Kilometre Array demonstrator being built in Oxford. If
you have any going spare, or would like to sell any, could you get in
contact with us at the email addresses listed above.
thanks and re
Hello,
My BEE2 is going to be deployed remotely. I need to use the Center FPGA for
my designs. Is there any way to remotely reprogram the Center FPGA (without
having to physically remove the CF card and put it in a card reader?) Can I
just program the new bit file using the JTAG header or will that
Hi John,
Are you running this arm() command on the BEE2 or are you using a udp or tcp
server? Does it write the value in ascii or binary mode? BORPH has
occasionally acted strangely for us when we use ascii mode so we don't use
it anymore.
Mark
On Fri, Jan 29, 2010 at 1:23 PM, John Ford wrote
> Hi John,
>
> Are you running this arm() command on the BEE2 or are you using a udp or
> tcp
> server?
There is a server on the bee2 that receives the arm() command from a
client and then executes it locally on the control FPGA.
> Does it write the value in ascii or binary mode?
Don't know. wil
All,
Does anyone have a mechanical drawing that depicts the dimensions of
the BEE2 mounting holes?
Thanks,
Jason
I haven't had exactly this problem, but I have had designs meet timing
and then changing just the slightest thing makes it miss timing by a
lot. I think the place and route is sort of heuristic, so just by
chance it gets an easy job some days and other days it spends hours
going in the wrong direct
Like Glenn has said, different routing within the FPGA can cause a
significant increase in the time needed to PAR. The IOBs for the
interchip links are pretty distributed through the chip, so changing
the target can make it harder to route. You can check the PAR logs
(system.log or implementation
All,
LBL has just received a BEE2 system that due to the 11 month delay in
delivery and subsequent acquisition of a BEE3 we no longer need. The
system arrived in good condition but has not been powered. If anyone has
an interest in acquiring this system, please let me know.
Thanks,
Dave
Dan,
When I offered up the PAPER BEE2's, you expressed interest.
There are now those, the one from LBNL (~$10k) and the
whizz one.
There's a v.likely $385k coming from USAF to ATA and
3rd beamformer desired. They can thus use 5 and a
spare makes sense, particularly if they can be
purchased at ~$1
Hi Glenn,
The .ace file is Linux-accessible at /cfgs. You can overwrite
it from within BORPH, then do a software reboot to load the new
bitstream.
Thanks,
Henry
G Jones wrote:
Hello,
My BEE2 is going to be deployed remotely. I need to use the Center FPGA
for my designs. Is there any way to re
hi jason,
i'm forwarding your request to dan burke,
who designed the bee2 enclosure and power supply.
dan b. might have a drawing that shows the bee2 board
mounting holes???
best,
dan
On 12/17/2010 7:52 AM, Jason Ray wrote:
All,
Does anyone have a mechanical drawing that depicts the dime
Thanks Dan!
Jason
At 11:13 AM 12/17/2010, Dan Werthimer wrote:
hi jason,
i'm forwarding your request to dan burke,
who designed the bee2 enclosure and power supply.
dan b. might have a drawing that shows the bee2 board
mounting holes???
best,
dan
On 12/17/2010 7:52 AM, Jason Ray wrote:
Thanks Dan.
That worked really well. Once the chassis is built to verify my
drawing is correct, I'll make it available to everyone.
Thanks again,
Jason
At 11:04 AM 12/20/2010, drbu...@berkeley.edu wrote:
The fastest way to get those numbers is to
open the Allegro PCB file and use the
line
Hi Shilpa and Glen,
The casper list is probably more appropriate (or at least more useful) for
this discussion, since the Parkes spectrometer is a CASPER design. I have
run into similar problems where a small design change makes the design not
route properly or meet timing. I'm not sure what the so
Hi,
In case there are BEE2 users who don't follow the BEE2
mailing lists...
Matt Dexter
-- Forwarded message --
Date: Mon, 5 Mar 2012 16:56:46 -0800 (PST)
From: Matt Dexter
To: BEE2 Users
Cc: bee2-maintain...@lists.berkeley.edu
Subject: Re: [bee2-users] BEE2 with a misbehavin
Hi Matt.
We've had failure of the connections at the BEE2 board itself. The
connectors lose their spring and oxidize. We just soldered the wires on
instead of changing the connectors.
For us the symptom was that the bee2 would boot up fine, but would fail
once a few of the FPGAs were loaded up
Greg,
Perhaps a CASPER maintainer can correct me if I'm wrong, but I believe I am
using the black box, because the files used are .ngo files. There is also a
"black box definition" bbd file. The pcore is called ddr2_controller_v2_00_a
if that helps any.
Thanks,
Glenn
On Mon, Sep 8, 2008 at 7:29 AM
Closer, but still not there yet... :-(
With the dcm_module version change I described earlier, the bof file
loads and I get a tinysh prompt instead of hanging (progress!). I
can read and write my registers as expected (so far) in tinysh
(progress!). My BORPH reads and writes via the /proc
On Jun 22, 2010, at 4:53 , Mikolaj Chwalisz wrote:
Hi Hayden,
I was able to reproduce system as Dave told. I have control fpga made
in 7.1 and user fpga made in 10.1. After dcm changes i have the same
results with some more comments. Reading and writing registers from
TinySH works as expected.
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