Re: [casper] Inter-chip connections problem

Hi all, The interchip busses on the BEE2 should be used with caution. The lines are wave-pipelined, and are routed in bundles that are not consistent throughout the board, or even within the same bus. You may have to play with different sending and capture phases on the different lines to get mor

Re: [casper] Inter-chip connections problem

> Matt, > > sorry, I had >> iii) external clock input to BEE was improved by Pierre & Henry and >> others, > then edited it > > should have left it ! > > thanks, > > Mel. > > > On 5/2/08, Matt Dexter wrote: >> Mel, >> >> Don't forget the effort we put in to deliver clean external clocks to >> Be

Re: [casper] Inter-chip connections problem

Mel, Don't forget the effort we put in to deliver clean external clocks to Beamformer's BEE2s. This scheme is an upgrade to the prototype scheme I got from the BWRC folks. Matt On Fri, 2 May 2008, melvyn wright wrote: > Hi Matt, > > > > On 5/2/08, Matt Dexter wrote: > > Didn't Aaron Parsons f

Re: [casper] Inter-chip connections problem

Didn't Aaron Parsons find that the BEE2's inter-FPGA buses have particular clock frequencies were it would work and others that it would not ? As I understood it there was some question about the on-board signal integrity of those signals. I don't know if the root problem was identified or not.

Re: [casper] Inter-chip connections problem

Hi, Jason, I've had similar experiences when sending time domain data from two IBOBs to one other FPGA (in this case it was non-CASPER hardware: the F board of the ATA/RAL correlator). I found that the XAUI links and accompanying async fifos can have slightly different latencies. Could t

[casper] Inter-chip connections problem

All, Randy and I are closing in one completing phase 1 of our pulsar machine. We have two iBOB samplers streaming samples over XAUI into the BEE2's FPGA1 and FPGA3, where the pfb & fft take place. Then we're using the inter-chip connections to pass the FFT bin values over to FPGA2 where the