<mailto:mschi...@nrao.edu>
315-316-2032
Matthew Schiller
*From:* 'Ross Martin' via casper@lists.berkeley.edu
*Sent:* Thursday, October 5, 2023 10:46 AM
*To:* casper
*Subject:* Re: [casper] PL data to PS DDR4 (AXI) {External}
DMA isn't always the best answer.
It's so
<mailto:mschi...@nrao.edu>
315-316-2032
Matthew Schiller
From: 'Ross Martin' via casper@lists.berkeley.edu
Sent: Thursday, October 5, 2023 10:46 AM
To: casper
Subject: Re: [casper] PL data to PS DDR4 (AXI) {External}
DMA isn't always the best answer.
It's someti
t;
>>
>>
>> FWIW: ngVLA plans to create functionality like this in “pure” hdl and
>> given the current effort to use more VHDL/Verilog blocks in casper ngVLA’s
>> work may be useful in the future. I hope to make progress on ngVLA’s
>> approach later this cale
n “pure” hdl and
> given the current effort to use more VHDL/Verilog blocks in casper ngVLA’s
> work may be useful in the future. I hope to make progress on ngVLA’s
> approach later this calendar year. But ngVLA is on Intel FPGAs so a porting
> process would still be required to get th
his
calendar year. But ngVLA is on Intel FPGAs so a porting process would still be
required to get that into Casper.
From: casper@lists.berkeley.edu On Behalf Of Ken
Semanov
Sent: Thursday, October 5, 2023 4:11 AM
To: casper@lists.berkeley.edu
Subject: [casper] PL data to PS DDR4 (AXI) {Exter
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