Back when I had a bigger design built using 10.1 libraries, I was able
to meet my timing constraits for a 1 GHz clock if I set the add delay
value to 6. I had a comment that this was overkill, but it not only
worked, but worked by an easy change in the mask instead of breaking
this mask and puttin
Using DSP48s with for addition with a latency of 2 yields the best timing
performance, from experience and Xilinx's recommendations, which is why it's
hard-coded.
-Suraj
On Thu, Jul 28, 2011 at 11:53 AM, Samuel Tun wrote:
> Yes, unchecking the DSP48 adders allows me to change the add latency.
>
Yes, unchecking the DSP48 adders allows me to change the add latency.
I had that option selected because it was one of the recommendations
towards meeting time constraints. I will test this out now and see.
Thanks for your help.
-Sam
On Thu, Jul 28, 2011 at 12:32 PM, Hong Chen wrote:
> Hi Sam,
Hi Sam,
Did you activate the 'DSP48 adders in butterfly' option in the
Implementation section? The add delay value will be fixed to 2 when that
option is on. Would you mind try turn off that and see if it works?
Thanks,
-Hong
On Thu, Jul 28, 2011 at 9:24 AM, Samuel Tun wrote:
> Hi,
>
> I am
Hi,
I am using the latest BWRC libraries in Linux, and I found that I
cannot change the add delay values in the FFT block mask. Back when I
was using the 10.1 libraries, changing this delay value along with
other parameters along the PFB chain allowed me to meet timing
constraints for a 1 GH
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