hi john,
as you suspected,
the samples from ADC083000 emerge eight at a time, from a single adc.
(not IQ).
the yellow block is badly labeled. the yellow block outputs should be
labled adc_sample_0 through adc_sample_7.
i'm not sure what time order the samples come out in.
i think mark and suraj also developed a yellow block for two interleaved
adc's
which outputs 16 samples per FPGA clock.
suraj, mark,
can you please change the labeling on the ADC yellow block.
and let john know the time order of the samples?
thanks,
dan
----------------------------------------------------------
Hi all. I'm looking at using this block, and the documentation doesn't
quite match up to the block. I'm using only zdok0.
The outputs on the block are labelled adc0_i0,adc0_q0, ...
,adc0_i3,adc0_q3.
Are these just demuxed output samples at 1/4 the clock frequency, like on
the ADC, or are they something else?
i.e. I set my adc clock for 800 MHz, and get 8 samples every 5 ns?
John
