Hi everyone,
I solved the problem.
在2022年11月10日星期四 UTC+8 15:26:11 写道：
> Hi Andrew,
>
> Thanks for your advice.
> I first set to the mlib_devel version of the build model to view the
> model.
> Then set the correct parameters on my device.
>
> cheers
> Wang
>
> 在2022年11月10日星期四 UTC+8 14:55:59 写
Hi Andrew,
Thanks for your advice.
I first set to the mlib_devel version of the build model to view the model.
Then set the correct parameters on my device.
cheers
Wang
在2022年11月10日星期四 UTC+8 14:55:59 写道：
> Hi Wang
>
> It may be that the version of the toolflow used to create that model, is
>
Hi Wang
It may be that the version of the toolflow used to create that model, is
not the same as what is on your machine. You may want to drag a new block
in from your library, and then set the parameters to the same as the block
in the model. There is also a script that will update the blocks in
Hi Wang
It looks like there is something going wrong during the creation of the
internal logic in the FFT.
Could you give us the following information
1. Which git repo and branch of mlib_devel are you using?
2. What parameters did you change on the FFT?
3. What are the first error messages you s
Hi Rolando,
I'll refer you to Xilinx Sysgen's reference documents. You should be able
to get them from their website. They contain all the info you need about
those blocks.
The different FFT versions will depend on your board - I'm not familiar
with the iBOB, so I'm not sure which FPGA it has on
Hi
In the attached picture you can see the fft xilinx blocks I found.
Which one should I use?
How should I set this block?
2016-01-20 3:06 GMT-06:00 Ryan Monroe :
> I don't use the stock CASPER FFTs anymore, but I'm pretty sure that
> there's no way to use them for anything less than {2 comple
I don't use the stock CASPER FFTs anymore, but I'm pretty sure that
there's no way to use them for anything less than {2 complex inputs
--OR-- 4 real inputs}. If you want less, you can drive an input with a
constant '0', but resource-wise, they're the same. This is because of
algorithmic limi
Hi Rolando,
I can't recall that it does, off the top of my head, but the Casper one can
be set up to use just one input. This is what I've done in the past, I
think.
Regards,
James
On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz wrote:
> Hi James and Andrew
>
> Thank for yours advices.
>
> I'm t
Hi James and Andrew
Thank for yours advices.
I'm trying to recompile the design of Peter McMahon:
https://casper.berkeley.edu/wiki/Parspec
I'm using these libraries:
https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20
and I use a virtual machine "windows XP SP3", on ubuntu 14
Hi Rolando
You may want to look at the Xilinx FFT for your use case. The CASPER FFT is
optimised so that minimal resources are used when processing high
bandwidths (either many inputs, or inputs captured at high sample rates).
In this case you may find that the Xilinx FFT actually uses fewer
resou
Hi Rolando,
Have you tried one of the built-in Xilinx FFTs? As far as I know, the
Casper ones really only exist because the Xilinx ones only accept one input
at a time.
If you do use them, they are really efficient with resources.
Regards,
James
On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz w
Hi
Is there any other FFT block that I can use with ADC4x250-8?
https://casper.berkeley.edu/wiki/ADC4x250-8
I am using the "fft_biplex_real_2x" block, however I need only one input of
the four that this block has. I placed at zero the others three inputs.
I need more FPGA resources from IBOB, a
Hi Rolando
Now, I need to understand the equalizer block.
After the FFT the size of each data sample has grown. Many astronomical
signals have a frequency spectrum that is related to white noise. This
means that each frequency channel sample is about the same size. So we
don't need lots of
On Sun, Aug 31, 2014 at 3:40 PM, Rolando Paz wrote:
> Hi again...
>
> I'm using a IBOB-QUADC, the FPGA clock rate is 200MHz, and QUADC clock
> rate is 200 MHz. The size of PFB and FFT is 2^11 pnts, and that means that
> I have 1024 channels for each of the four inputs of the QUADC, is this
> corr
Hi again...
I'm using a IBOB-QUADC, the FPGA clock rate is 200MHz, and QUADC clock rate
is 200 MHz. The size of PFB and FFT is 2^11 pnts, and that means that I
have 1024 channels for each of the four inputs of the QUADC, is this
correct?
My correlation block is called "xengine4", and within are 6
i think the FFT biplex real 2x block
can compute real to complex FFT's on
4, 8, 12, 16 inputs, depending on how you set
the "Number simultaneous inputs" parameter.
best wishes,
dan
On Sun, Aug 31, 2014 at 10:26 AM, Rolando Paz wrote:
> Hi Dan
>
> Now I understand :-)
>
> It's very d
Hi Dan
Now I understand :-)
It's very different this:
4 time samples in parallel (fft_wideband_real)
4 real streams (fft_biplex_real_2x)
Casper's website says (https://casper.berkeley.edu/wiki/Fft_biplex_real_2x):
...Thus, a biplex core (which can do 2 complex FFTs) can transform 4 real
str
hi Rolando,
the quad adc outputs one sample per FPGA clock,
so your correlator will need to use an FFT with real input,
complex output, 1 real input sample per clock.
I think (but I'm not sure), the *fft_biplex_real_2x block does*
*two real to complex ffts, so you'll need*
*two of these blocks to
Could someone please explain why the QUADC designs use only the
fft_bliplex_real_2x block?
Why the fft_biplex_real_2x block uses more resources than the
fft_wideband_real block?
Best Regards
Rolando Paz
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